Calculation of stress probability for NBTI-aware timing analysis

Stempkovsky, A. L.; Glebov, A.; Gavrilov, S. V.

doi:10.1109/isqed.2009.4810381

Cited by 16 publications

(12 citation statements)

References 7 publications

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“…Signal probability propagation has been studied extensively in the field of power analysis [15] and NBTI-related probability propagation [16]. In this paper, a similar approach is taken in calculating the propagation of signal probabilities from the primary inputs.…”

Section: Dataset and Empirical Variablesmentioning

confidence: 99%

Identification and Application of Invariant Critical Paths under NBTI Degradation

Bian

Morita

Shintani

et al. 2017

IEICE Trans. Fundamentals

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SUMMARYAs technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain. key words: NBTI, aging effect, invariant critical path, processor

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Section: Dataset and Empirical Variablesmentioning

confidence: 99%

Identification and Application of Invariant Critical Paths under NBTI Degradation

Bian

Morita

Shintani

et al. 2017

IEICE Trans. Fundamentals

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“…The output of the VCS-VPI program is the switching activities for all the pins on the target critical paths. Based on this switching information, equivalent stress signals [Kumar et al 2006;Stempkovsky et al 2009] are generated for each pin on the critical paths. This can be easily performed by generating a large number of patterns, representing workload, to apply to the circuit and then calculating the switching probability of the target pins.…”

Section: Apd Analysis Flowmentioning

confidence: 99%

Critical-reliability path identification and delay analysis

Chen

Wang

Tehranipoor

2014

J. Emerg. Technol. Comput. Syst.

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Circuit reliability analysis at the presilicon stage has become vital for sub-45nm technology designs in particular, due to aging effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). To avoid potential reliability hazards in the postsilicon stage, current large-scale designs for commercial implementation overpessimistically analyze circuit aging under assumed worst-case workload in order not to violate the corner cases even for low possibilities, thus introducing unnecessary margin in the design timing analysis. The major issue is lack of an effective aging analysis method applicable to large designs with low CPU runtime, which is mainly due to: (1) conventional reliability tools are extremely timeconsuming for circuit-level timing analysis and thus are not practical for large designs; (2) mathematical models developed to expedite the process are not accurate due to the high complexity of aging effects. In this article, a comprehensive analysis is presented to highlight the importance of each aging parameter. Then, a novel methodology is developed based on current commercial reliability tools to guarantee its high accuracy on circuit-level aging analysis. Existing proven low-level mathematical models are further enhanced to extensively speed up a higher level analysis by taking advantage of the explicit intermediate conditions stored in a pregenerated lookup table. Our results indicate ≥244X improved computational efficiency, ≤5% relative error, and ≤0.7% absolute error compared with commercial reliability analysis tools (e.g., HSPICE MOSRA).

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“…However, no formal way is described to calculate them. In [16] no aging-aware gate model is proposed, but an algorithm to compute the time each individual transistor of a gate is in stress condition. It also considers signal correlation at the gate inputs.…”

Section: Gate Level Aging Analysismentioning

confidence: 99%

“…When the transistor is conducting (condition A fulfilled) it is enough to have a logic ''1'' at the source (drain) terminal, since the drain (source) terminal will be charged to the same value. Condition B is fulfilled if a conducting path exists between the supply voltage V DD and the source or drain terminal [16] of the transistor M. Hence, all PMOS transistors along the conducting path must have a logic ''0'' applied to their gate terminals as well. There might be multiple paths from V DD to the source or drain terminal of a transistor (see Fig.…”

Section: Stress Probability For Nbtimentioning

confidence: 99%