CacheQuery: learning replacement policies from hardware caches

Vila, Pepe; Ganty, Pierre; Guarnieri, Marco; Köpf, Boris

doi:10.1145/3385412.3386008

Cited by 30 publications

(24 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another relevant issue is investigating a learned strategy [33][34][35] to implement the adaptive mechanism in AMG-Buffer. It has been a hot topic in recent years to use machine learning models for optimizing database components [36].…”

Section: Discussionmentioning

confidence: 99%

Adaptive Multi-Grained Buffer Management for Database Systems

Wang

Jin

2021

Future Internet

View full text Add to dashboard Cite

The traditional page-grained buffer manager in database systems has a low hit ratio when only a few tuples within a page are frequently accessed. To handle this issue, this paper proposes a new buffering scheme called the AMG-Buffer (Adaptive Multi-Grained Buffer). AMG-Buffer proposes to use two page buffers and a tuple buffer to organize the whole buffer. In this way, the AMG-Buffer can hold more hot tuples than a single page-grained buffer. Further, we notice that the tuple buffer may cause additional read I/Os when writing dirty tuples into disks. Thus, we introduce a new metric named clustering rate to quantify the hot-tuple rate in a page. The use of the tuple buffer is determined by the clustering rate, allowing the AMG-Buffer to adapt to different workloads. We conduct experiments on various workloads to compare the AMG-Buffer with several existing schemes, including LRU, LIRS, CFLRU, CFDC, and MG-Buffer. The results show that AMG-Buffer can significantly improve the hit ratio and reduce I/Os compared to its competitors. Moreover, the AMG-Buffer achieves the best performance on a dynamic workload as well as on a large data set, suggesting its adaptivity and scalability to changing workloads.

show abstract

Section: Discussionmentioning

confidence: 99%

Adaptive Multi-Grained Buffer Management for Database Systems

Wang

Jin

2021

Future Internet

View full text Add to dashboard Cite

show abstract

“…As a consequence, eviction-based side channels such as Evict+ Reload, Evict+Time, Prime+Probe, or Reload+Refresh are not detected. However, related work [34,94,95] showed that eviction strategies can also be found automatically. Moreover, for specific problems, the search space can be reduced by mutating existing instruction sequences (similar to Medusa [65]) or instruction operands instead of randomly generating them.…”

Section: Discussionmentioning

confidence: 99%

Osiris: Automated Discovery of Microarchitectural Side Channels

Weber,

Ibrahim,

Nemati

et al. 2021

Preprint

View full text Add to dashboard Cite

In the last years, a series of side channels have been discovered on CPUs. These side channels have been used in powerful attacks, e.g., on cryptographic implementations, or as building blocks in transient-execution attacks such as Spectre or Meltdown. However, in many cases, discovering side channels is still a tedious manual process.In this paper, we present Osiris, a fuzzing-based framework to automatically discover microarchitectural side channels. Based on a machine-readable specification of a CPU's ISA, Osiris generates instruction-sequence triples and automatically tests whether they form a timing-based side channel. Furthermore, Osiris evaluates their usability as a side channel in transient-execution attacks, i.e., as the microarchitectural encoding for attacks like Spectre. In total, we discover four novel timing-based side channels on Intel and AMD CPUs. Based on these side channels, we demonstrate exploitation in three case studies. We show that our microarchitectural KASLR break using non-temporal loads, FlushConflict, even works on the new Intel Ice Lake and Comet Lake microarchitectures. We present a cross-core cross-VM covert channel that is not relying on the memory subsystem and transmits up to 1 kbit/s. We demonstrate this channel on the AWS cloud, showing that it is stealthy and noise resistant. Finally, we demonstrate Stream+Reload, a covert channel for transientexecution attacks that, on average, allows leaking 7.83 bytes within a transient window, improving state-of-the-art attacks that only leak up to 3 bytes.

show abstract

“…Recent measurement-based approaches [1,2,65] to automatically derive cache models are also naturally limited to models satisfying data independence. Our warping cache simulator supports LRU, FIFO, PLRU [3], and Quad-age LRU [39,40], which allows to model the L1 and L2 caches of most recent Intel microarchitectures [2,65]. Other policies can be added as long as they satisfy data independence.…”

Section: Cache Setsmentioning

confidence: 99%

“…Traditional cache simulators, such as Dinero IV [20] or CASPER [38], simulate a program's cache behavior by explicitly iterating over the trace of memory accesses generated by the program. The advantage of this approach is that it is applicable to arbitrary workloads and it is possible to precisely model modern memory hierarchies, including sophisticated cache replacement policies, such as Pseudo-LRU [3] or Quad-age LRU [39,40] found in real-world microarchitectures [2,65]. The main drawback of traditional simulators is that their runtime is proportional to the number of memory accesses a program performs.…”

Section: Introductionmentioning

confidence: 99%

Warping Cache Simulation of Polyhedral Programs

Morelli¹,

Reineke²

2022

Preprint

View full text Add to dashboard Cite

Techniques to evaluate a program's cache performance fall into two camps: 1. Traditional trace-based cache simulators precisely account for sophisticated real-world cache models and support arbitrary workloads, but their runtime is proportional to the number of memory accesses performed by the program under analysis. 2. Relying on implicit workload characterizations such as the polyhedral model, analytical approaches often achieve problem-size-independent runtimes, but so far have been limited to idealized cache models.We introduce a hybrid approach, warping cache simulation, that aims to achieve applicability to real-world cache models and problem-size-independent runtimes. As prior analytical approaches, we focus on programs in the polyhedral model, which allows to reason about the sequence of memory accesses analytically. Combining this analytical reasoning with information about the cache behavior obtained from explicit cache simulation allows us to soundly fast-forward the simulation. By this process of warping, we accelerate the simulation so that its cost is often independent of the number of memory accesses.CCS Concepts: • Software and its engineering → Software performance; Automated static analysis.

show abstract

CacheQuery: learning replacement policies from hardware caches

Cited by 30 publications

References 29 publications

Adaptive Multi-Grained Buffer Management for Database Systems

Adaptive Multi-Grained Buffer Management for Database Systems

Osiris: Automated Discovery of Microarchitectural Side Channels

Warping Cache Simulation of Polyhedral Programs

Contact Info

Product

Resources

About