Cache vulnerability equations for protecting data in embedded processor caches from soft errors

Abstract

Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, caches are most vulnerable to soft errors, and techniques at various levels of design abstraction, e.g., fabrication, gate design, circuit design, and microarchitecture-level, have been developed to protect data in caches. However, no work has been done to investigate the effect of code transformations on the vulnerability of data in caches. Data is vulnerable to soft errors in the cache only if it will be read by the processor, and not if it will be overwritten. Since code transformations can change the read-write pattern of program variables, they significantly effect the soft error vulnerability of program variables in the cache. We observe that often opportunity exists to significantly reduce the soft error vulnerability of cache data by trading-off a little performance. However, even if one wanted to exploit this trade-off, it is difficult, since there are no efficient techniques to estimate vulnerability of data in caches. To this end, this paper develops efficient static analysis method to estimate program vulnerability in caches, which enables the compiler to exploit the performance-vulnerability trade-offs in applications. Finally, as compared to simulation based estimation, static analysis techniques provide the insights into vulnerability calculations that provide some simple schemes to reduce program vulnerability.

Thread vulnerability in parallel applications

“…Both RVF and CVF values are calculated by considering susceptible times of register values and cache blocks respectively. [28] has also proposed a static analysis method to estimate program vulnerability in caches.…”

Pica

“…In this article, we present steady-state analysis of the data in the cache for several kinds of loops and increase the applicability and effectiveness of the PICA approach by answering the question of "when to prefetch." While there are elaborate analytical models on cache behavior [Chatterjee et al 2001;Ghosh et al 1997;Shrivastava et al 2010;Verdoolaege et al 2007], none of them are widely used today, as they have practical limitations, such as high computational complexity and limited architectural features supported. Moreover, our problem is more complex than cache modeling, because it also involves hardware prefetching and multiple processor states.…”

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

“…Previous studies [22][23][24] have shown that implementing SEC-DED can increase L1 cache access latency by up to 95%, and power consumption by up to 22%.…”

“…Moreover, protecting higher levels of cache (e.g., L1 data cache (L1D)) using ECC would induce higher overheads. Previous studies showed that single-error correction and doubleerror detection (SEC-DED) in L1 cache would increase its access latency by up to 95%, power consumption by up to 22%, and area cost by up to 18% [22][23][24] . A variety of techniques have been proposed to reduce the area, performance and power costs of ECC [25][26][27][28][29][30] .…”