Cache persistence analysis

Cullmann, Christoph

doi:10.1145/1967677.1967695

Cited by 9 publications

(11 citation statements)

References 14 publications

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“…RELATED WORK Abstract interpretation based single-level cache analysis has been widely used in WCET analysis [19]. However, it has been found its original persistence analysis is not safe, and the safe persistence analysis is proposed in [5,10]. The first multilevel cache analysis is proposed in [16], which is an extension to another well-established single-level cache analysis method called static cache simulation [17].…”

Section: Discussionmentioning

confidence: 99%

“…In order to make the analysis scalable, most of the approaches are based on abstract interpretation. An abstract interpretation based approach aims to assign a cache hit/miss classification (CHMC) to each memory reference according to the abstract cache states (ACSs) derived by three different analyses [19,5]. The analyses are usually performed on the control-flow graph (CFG) reconstructed from the low-level code of the program.…”

Section: Problem Statementmentioning

confidence: 99%

“…As described in [19], an abstract cache state is a mapping from a cache set number to an abstract set state, where an abstract set state is a mapping from a position to a set of memory blocks. [10] or [5].…”

Section: System Modelmentioning

confidence: 99%

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Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-In many multi-core architectures, inclusive shared caches are used to reduce cache coherence complexity. However, the enforcement of the inclusion property can cause invalidation of memory blocks at higher cache levels. In order to ensure safety, analysis of cache hierarchies with inclusive caches for worst-case execution time (WCET) estimation is typically based on conservative decisions. Thus, the estimation may not be tight. In order to tighten the estimation, this paper proposes an approach that can more precisely analyze the behavior of a cache hierarchy maintaining the inclusion property. We illustrate the approach in the context of multi-level instruction caches. The approach first analyzes all the inclusive caches in the hierarchy in a bottom-up direction, and then analyzes the remaining non-inclusive caches in a top-down direction. In order to capture the inclusion victims and their effects, we also propose a concept of aging barrier and integrate it with the traditional must and persistence analyses to safely slow down their aging process so as to derive more precise analyses. We evaluate the proposed approach on a set of benchmarks and the evaluation reveals that the estimations are tightened.

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Section: Discussionmentioning

confidence: 99%

Section: Problem Statementmentioning

confidence: 99%

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Top-down and bottom-up multi-level cache analysis for WCET estimation

Zhang

Koutsoukos

2015

21st IEEE Real-Time and Embedded Technology and Applications Symposium

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“…The ability to profile and analyze the key aspects of applications' memory access patterns is a turning point in the optimization of cache management techniques. A body of works exists that use abstract interpretation [Cousot 2001;Cullmann 2013], symbolic execution [King 1976], hardware and software memory tracing [Sun and Tian 2011;Xiaofeng et al 2005;Cesati et al 2015] to gather information about memory access patterns. These techniques have been mostly used to perform static analysis.…”

Section: Future Directionsmentioning

confidence: 99%

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

et al. 2015

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Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power. However, multicore processors have shared resources that affect the predictability of real-time systems, which is the key to correctly estimate the worst-case execution time of tasks. One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy. Recently, many research works have proposed different techniques to deal with caches in multicore processors in the context of real-time systems. Nevertheless, a review and categorization of these techniques is still an open topic and would be very useful for the real-time community. In this article, we present a survey of cache management techniques for real-time embedded systems, from the first studies of the field in 1990 up to the latest research published in 2014. We categorize the main research works and provide a detailed comparison in terms of similarities and differences. We also identify key challenges and discuss future research directions.

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“…While the must and may analyses are safe, it has been known that the original persistence analysis method proposed in [7] is unsafe. Several approaches have been proposed to ensure safe cache persistence analysis [5,6,11]. However, different approaches may suffer from certain pessimism under different scenarios (i.e.…”

Section: Introductionmentioning

confidence: 99%

Improving the Precision of Abstract Interpretation Based Cache Persistence Analysis

Zhang

Koutsoukos

2015

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM

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When designing hard real-time embedded systems, it is required to estimate the worst-case execution time (WCET) of each task for schedulability analysis. Precise cache persistence analysis can significantly tighten the WCET estimation, especially when the program has many loops. Methods for persistence analysis should safely and precisely classify memory references as persistent. Existing safe approaches suffer from multiple sources of pessimism and may not provide precise results. In this paper, we first identify some sources of pessimism that two recent approaches based on younger set and may analysis may encounter. Then, we propose two methods to eliminate these sources of pessimism. The first method improves the update function of the may analysis-based approach; and the second method integrates the younger set-based and may analysis-based approaches together to further reduce pessimism. We also prove the two proposed methods are still safe. We evaluate the approaches on a set of benchmarks and observe the number of memory references classified as persistent is increased by the proposed methods. Moreover, we empirically compare the storage space and analysis time used by different methods.

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Cache persistence analysis

Cited by 9 publications

References 14 publications

Top-down and bottom-up multi-level cache analysis for WCET estimation

Top-down and bottom-up multi-level cache analysis for WCET estimation

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

Improving the Precision of Abstract Interpretation Based Cache Persistence Analysis

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