Cache Misses and the Recovery of the Full AES 256 Key

Abstract

The CPU cache is a hardware element that leaks significant information about the software running on the CPU. Particularly, any application performing sequences of memory access that depend on sensitive information, such as private keys, is susceptible to suffer a cache attack, which would reveal this information. In most cases, side-channel cache attacks do not require any specific permission and just need access to a shared cache. This fact, combined with the spread of cloud computing, where the infrastructure is shared between different customers, has made these attacks quite popular. Traditionally, cache attacks against AES use the information about the victim to access an address. In contrast, we show that using non-access provides much more information and demonstrate that the power of cache attacks has been underestimated during these last years. This novel approach is applicable to existing attacks: Prime+Probe, Flush+Reload, Flush+Flush and Prime+Abort. In all cases, using cache misses as source of information, we could retrieve the 128-bit AES key with a reduction in the number of samples of between 93% and 98% compared to the traditional approach. Further, this attack was adapted and extended in what we call the encryption-by-decryption cache attack (EBD), to obtain a 256-bit AES key. In the best scenario, our approach obtained the 256 bits of the key of the OpenSSL AES T-table-based implementation using fewer than 10,000 samples, i.e., 135 milliseconds, proving that AES-256 is only about three times more complex to attack than AES-128 via cache attacks. Additionally, the proposed approach was successfully tested in a cross-VM scenario.

Detecting Time-Fragmented Cache Attacks Against AES Using Performance Monitoring Counters

“…Time-driven attacks against the shared and inclusive Last Level Cache (LLC) are mainly based on Flush&Reload [14] and their variants. So, both [1] and [4] extract the key from the AES T-table based encryption algorithm using improvements over the original attack.…”

“…In Section 2, we exposed previous algorithms for extraction of the AES key. We use the approach of [4] to break the OpenSSL 1.1.1.b AES 128 bits implementation (this library has had to be compiled with no-asm flag, so that it uses the T-Tables implementation). The attack begins by forcing the de-duplication of library pages (see Section 3.2).…”

Cloud Computing and Big Data

“…Time-driven attacks against the shared and inclusive Last Level Cache (LLC) are mainly based on Flush&Reload [15] and their variants. So, Briongos [4] extracts the key from the AES T-table based encryption algorithm using improvements over the original attack.…”

Special Issue on “Side Channel Attacks”

“…One paper proposes a new constant-time method for RSA modular exponentiation, which is resistant against fine-grained cache attacks [66]. The other one shows a non-access attack, a novel approach for exploiting the information gained from cache misses [67].System-level counter-measures and their weaknesses: Two research papers in this special issue introduce a new system-level counter-measure and a new vulnerability of the existing physically un-clonable function (PUF), respectively. One paper deals with the re-keying scheme, a system-level counter-measure against SCAs, which makes attackers unable to collect enough power consumption traces for their analyses [68].…”

“…One paper proposes a new constant-time method for RSA modular exponentiation, which is resistant against fine-grained cache attacks [66]. The other one shows a non-access attack, a novel approach for exploiting the information gained from cache misses [67].…”