Cache Coherence Protocols for Many-Core CMPs

Ros, Alberto; Acacio, Manuel E.; García, José M.

doi:10.5772/9454

Cited by 16 publications

(10 citation statements)

References 47 publications

(42 reference statements)

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“…This is an optimistic approach using potentially failing requests, enabling a fast common case. The DicoCMP protocol and its variants [17], [18] store the sharers in both the L1 and the L2 caches. The approach used consists in that a requesting writer L1 cache must send invalidations directly to the other L1 cache owning a copy instead of the L2 cache (home tile), at the price of tracking the list of sharers for each line in the L1 caches.…”

Section: Related Workmentioning

confidence: 99%

RWT: Suppressing Write-Through Cost When Coherence is Not Needed

Líu

Dévigne

Garcia

et al. 2015

2015 IEEE Computer Society Annual Symposium on VLSI

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In shared-memory multicore architectures, handling a write cache operation is more complicated than in singleprocessor systems. A cache line may be present in more than one private L1 cache. Any cache willing to write this line must inform all the other sharers. Therefore, it is necessary to implement a cache coherence protocol for multicore architectures.At present, directory based protocols are popular cache coherence protocols in both industry and academic domains because of their reduced coherence traffic compared to snooping protocols, at the expense of an indirection. The write policy -write through or write back -is crucial in the protocol design.The write-through policy reduces the bandwidth because it augments the write traffic in the interconnection network, and also augments the energy consumption. However, it can efficiently solve the false sharing problem via write updates. In this paper, we introduce a new way to reduce the write traffic of a write-through coherence protocol by combining write-through coherence with a write-back policy for non coherent lines. The baseline write-through used as reference is a scalable hybrid invalidate/update protocol.Simulation results show that with our enhanced protocol, we can reduce at least by 50% the write traffic in the interconnection network, and gain up to 20% performance compared with the baseline write-through protocol.

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Section: Related Workmentioning

confidence: 99%

RWT: Suppressing Write-Through Cost When Coherence is Not Needed

Líu

Dévigne

Garcia

et al. 2015

2015 IEEE Computer Society Annual Symposium on VLSI

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“…As an immediate consequence, the memory subsystem has to evolve into some novel organization that overcomes the problems of traditional cache-based schemes. Two of the major concerns are the important amount of power consumed in the cache hierarchy and the lack of scalability of current cache coherence protocols, which constrain the sharing and the size of caches when cores are replicated beyond certain levels [1], [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Hardware-software coherence protocol for the coexistence of caches and local memories

Alvarez¹,

Vilanova²,

González³

et al. 2012

2012 International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and do not generate coherence traffic, but they suffer from poor programmability. When non-predictable memory access patterns are found compilers do not succeed in generating code because of the incoherence between the two storages. This paper proposes a coherence protocol for hybrid memory systems that allows the compiler to generate code even in the presence of memory aliasing problems. Coherence is ensured by a software/hardware co-design where the compiler identifies potentially incoherent memory accesses and the hardware diverts them to the correct copy of the data. The coherence protocol introduces overheads of 0.26% in execution time and of 2.03% in energy consumption to enable the usage of the hybrid memory system, which outperforms cache-based systems by an speedup of 38% and an energy reduction of 27%.

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“…Directory-based protocols [12] reduce network traffic as directory structure allows to store information about the private caches state. However, these traditional cache coherence protocols introduce indirection in the critical path of cache misses [13]. To solve the problem of indirection, Token-CMP [14] and DiCo-CMP [15] protocols have been proposed.…”

Section: Related Workmentioning

confidence: 99%

“…These indirection-aware protocols avoid the access to the home node allowing latency of cache misses to be reduced. All these protocols (Hammer, Directory-based, Dico-CMP, and Token-CMP) can be implemented over non-ordered interconnects [13], and therefore, avoiding the use of costly interconnection architectures. However, the inherent costs of these proposals are not negligible.…”

Section: Related Workmentioning

confidence: 99%

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-onchip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol -and hence its resources -, and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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Cache Coherence Protocols for Many-Core CMPs

Cited by 16 publications

References 47 publications

RWT: Suppressing Write-Through Cost When Coherence is Not Needed

RWT: Suppressing Write-Through Cost When Coherence is Not Needed

Hardware-software coherence protocol for the coexistence of caches and local memories

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

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