C Based Hardware Design for Wireless Applications

Takach, Andrés; Bowyer, Bryan; Bollaert, Thomas

doi:10.1109/date.2005.87

Cited by 19 publications

(11 citation statements)

References 2 publications

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“…code and worked to optimize the implementation through the HLS tool flow. Similar approaches were followed in [12][13][14] for algorithms that had lower complexity or lower throughput requirements. In [12], the PICO high level synthesis tool was employed to implement image processing kernels.…”

Section: Related Workmentioning

confidence: 91%

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Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

Noguera

Neuendorffer

Haastregt

et al. 2011

Analog Integr Circ Sig Process

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In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C?? descriptions as input specifications, and automatically generate a register transfer level (RTL) description for FPGA implementation using traditional FPGA implementation tools. We have used AutoESL's AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225 MHz. The obtained results show that these modern HLS tools produce Quality of Results competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details.

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Section: Related Workmentioning

confidence: 91%

“…In [12], the PICO high level synthesis tool was employed to implement image processing kernels. In [13], the Catapult-C high level synthesis tool was employed to implement a 64-QAM decoder in both FPGA and ASIC technology. In [14], the Impulse C tool suite was employed to implement a computed tomography back-projection algorithm.…”

Section: Related Workmentioning

confidence: 99%

Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

Noguera

Neuendorffer

Haastregt

et al. 2011

Analog Integr Circ Sig Process

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“…Simulators have to sacrifice simulation speed for full VHDL compliance. MentorGraphics CatapultC [2] generates VHDL from pure C++ especially aiming at dataflow oriented applications. Celoxica offers its Handel-C language for the same purpose.…”

Section: Requirementsmentioning

confidence: 99%

C/VHDL codesign for LHCb VELO zero suppression algorithms

Muecke

2005

14th IEEE-NPSS Real Time Conference, 2005.

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Abstract-We present a workflow to generate cycle-accurate C and VHDL code from one common description to accelerate and unify algorithm implementation and simulation for real-time DSP applications in particle detectors.We use Confluence as description language which compiles into C-code (for simulation) and VHDL code (for implementation on FPGAs). We demonstrate the improved portability and simulation speed while assuring bit-and cycle-accuracy. Our approach solves the problem of having to maintain two source codes (for simulation and implementation) in parallel and therefore minimizes workload and the danger of inconsistent models. This is crucial in an environment where algorithm implementation is expected to cycle through several design iterations.

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“…C-to-gates synthesis is a maturing field with notable systems-see [6], [7], [13], [18], [21], [26], [32], [33]. Some existing C-to-gates synthesis systems already support pointers and pointer aliasing, see e.g.…”

Section: Introductionmentioning

confidence: 99%

Finding heap-bounds for hardware synthesis

Cook¹,

Gupta

Magill³

et al. 2009

2009 Formal Methods in Computer-Aided Design

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Abstract-Dynamically allocated and manipulated data structures cannot be translated into hardware unless there is an upper bound on the amount of memory the program uses during all executions. This bound can depend on the generic parameters to the program, i.e., program inputs that are instantiated at synthesis time. We propose a constraint based method for the discovery of memory usage bounds, which leads to the firstknown C-to-gates hardware synthesis supporting programs with non-trivial use of dynamically allocated memory, e.g., linked lists maintained with malloc and free. We illustrate the practicality of our tool on a range of examples.

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C Based Hardware Design for Wireless Applications

Abstract: Abstract

Cited by 19 publications

References 2 publications

Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

C/VHDL codesign for LHCb VELO zero suppression algorithms

Finding heap-bounds for hardware synthesis

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