C-axis aligned crystalline indium–gallium–zinc oxide ceramics and oxide semiconductor LSI as countermeasures against global warming

Yamazaki, Shunpei; Kimura, Kiyoshi; Onuki, Tatsuya; Shimada, Daigo; Kimura, Hajime; Isaka, Fumito; Hodo, Ryota; Baba, H.; Nakayama, Teruo; Kunitake, Hitoshi

doi:10.1016/j.ceramint.2022.10.050

Cited by 2 publications

(2 citation statements)

References 31 publications

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“…The channel-shortening effect, which is typically attributed to the increased carrier concentration resulting from the presence of oxygen vacancy (VO) and VOH formation, is not observed in the as-grown C-IGZO TFT with a channel length of 1.16 µm (13). The hysteresis-free characteristics of the as-grown C-IGZO TFT can be seen in Fig.…”

Section: Resultsmentioning

confidence: 99%

80‐4: Highly Reliable, As‐Grown Crystalline InGaZnO TFTs by Spray Pyrolysis for Low‐Cost Manufacturing of High‐Resolution AMOLED Display

Bae,

Ali,

Islam

et al. 2024

Symp Digest of Tech Papers

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We report a low‐cost method for growing highly‐oriented crystalline InGaZnO (C‐IGZO) for a high‐resolution, active‐matrix thin‐film transistor (TFT) backplane for organic light‐emitting diode displays using spray pyrolysis. The self‐aligned, coplanar oxide TFT with an as‐grown C‐IGZO channel layer demonstrates a threshold voltage of‐0.35 V, saturation mobility of 33.99 cm2 V‐1 s‐1 , and subthreshold swing of 0.15 Vdec‐1, with an on/off current ratio exceeding 108 . Moreover, the C‐IGZO TFT with a channel length of 1.16 μm exhibits excellent operational stability under bias temperature stress.

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Section: Resultsmentioning

confidence: 99%

80‐4: Highly Reliable, As‐Grown Crystalline InGaZnO TFTs by Spray Pyrolysis for Low‐Cost Manufacturing of High‐Resolution AMOLED Display

Bae,

Ali,

Islam

et al. 2024

Symp Digest of Tech Papers

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“…2. The planar FET has a shape similar to that of previously reported OSFETs and has been used in various applications [14], [15], [16], [17]. The planar FET includes a bottom gate (BG) electrode and a top gate (TG) electrode; the threshold voltage (Vth) of the planar FET can be controlled by varying the BG voltage [7].…”

Section: Introductionmentioning

confidence: 95%

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

Hirose,

Okamoto,

Komura

et al. 2024

IEEE J. Electron Devices Soc.

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We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an 2.2  10 -19 A/cell at 85C), indicating that over 99 of the data are retained in the memory array after one hour at 85C without refresh.

show abstract

C-axis aligned crystalline indium–gallium–zinc oxide ceramics and oxide semiconductor LSI as countermeasures against global warming

Cited by 2 publications

References 31 publications

80‐4: Highly Reliable, As‐Grown Crystalline InGaZnO TFTs by Spray Pyrolysis for Low‐Cost Manufacturing of High‐Resolution AMOLED Display

80‐4: Highly Reliable, As‐Grown Crystalline InGaZnO TFTs by Spray Pyrolysis for Low‐Cost Manufacturing of High‐Resolution AMOLED Display

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

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