Bump heat sink technology - A novel assembly technology suitable for power HBTs

Sato, H.; Miyauchi, M.; Sakuno, K.; Akagi, Masataka; Hasegawa, M.; Twynam, J.K.; Yamamura, Keiji; Tomita, Takashi

doi:10.1109/gaas.1993.394439

Cited by 18 publications

(5 citation statements)

References 6 publications

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“…Several Structure modification approaches have been proposed to obtain a lower temperature, such as reducing the substrate thickness, increasing fingers' spacing and introducing heat sink via [4]. Then, the uniformity of DC and drive levels for the paralleled cells of large power devices becomes the hot spot.…”

Section: Introductionmentioning

confidence: 99%

Thermal analysis and design of peripheral adaption power cell for power amplifier

Sun

2014

2014 International Conference on Information Science, Electronics and Electrical Engineering

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Peripheral adaption power cell networks are designed to make the power cell open gradually with the increasing input power. The pre-determined emitter ballast resistors are used to perform the adaption operation. Power consumption then reduces especially for the center fingers with larger emitter ballast resistors. As a result, the novel power cell appears a reverse bell-alike temperature distribution different from traditional power cells. Finger spacing is further optimized to obtain a uniform temperature distribution which makes the distributed matching circuit more efficient. With this thermal design, the power amplifier shows an excellent output power of 33 dBm with PAE of 50%.

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Section: Introductionmentioning

confidence: 99%

Thermal analysis and design of peripheral adaption power cell for power amplifier

Sun

2014

2014 International Conference on Information Science, Electronics and Electrical Engineering

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“…Pervasive examples are the collapse of current gain affecting multi‐finger GaAs HBTs, which can be SOA‐limiting or even destructive, the discrepancy between dynamic and static error vector magnitude, thermal memory effects, and reliability/ruggedness issues in GaAs HBT PAs. Since the late 80s a plethora of papers have been published, which deal with the thermal or ET behavior of single‐ and multi‐finger transistors as well as of circuits in GaAs technology (representative ones being). Many studies focused on the metallization due to the important role played by the upward heat flow in this technology (the low thermal conductivity of the GaAs substrate mitigates the downward flow to the backside).…”

Section: Introductionmentioning

confidence: 99%

“…Other works dealing with multi‐finger transistors have promoted emitter or base ballasting and nonuniform finger spacing or length for assigned die and emitter areas . Some papers have also studied the beneficial effect of a thermally‐conductive and/or shorter path from the heat dissipation region to the sink, which can be obtained with flip‐chip packaging or alternative strategies based on thermal vias …”

Section: Introductionmentioning

confidence: 99%

Accurate and efficient analysis of the upward heat flow in InGaP/GaAs HBTs through an automated FEM‐based tool and Design of Experiments

d’Alessandro

Catalano

Codecasa

et al. 2018

Int J Numerical Modelling

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This paper presents an extensive analysis aimed at quantifying the impact of all the key technology parameters on the upward heat flow in state-of-the-art InGaP/GaAs heterojunction bipolar transistors (HBTs) for various emitter areas and shapes. Extremely accurate thermal simulations are conducted in a relatively short time with a tool relying on a commercial 3-D finite-element method (FEM) solver and an in-house routine for automated geometry construction, optimized mesh generation, sequential solution, and data storing/processing. Design of Experiments is used to define a thermal resistance model as a function of the aforementioned parameters on the basis of a few FEM data. also studied the beneficial effect of a thermally-conductive and/or shorter path from the heat dissipation region to the sink, which can be obtained with flip-chip packaging 13,14,19,20,22,30 or alternative strategies based on thermal vias. 17,32 Unfortunately, almost all the thermal analyses presented in the above papers are (sometimes unacceptably) inaccurate: the real-and complex-device structures are always represented with simplified (or even oversimplified) domains to allow (1) the development of analytical models for the temperature distribution or (2) an easy construction/meshing of the 3-D geometry for numerical simulations; still now, in spite of the continuous improvement in PC performances, task (2) is not trivial if performed manually, especially when all technological details must be taken into account.Recently, the upward heat flow has been given attention in some works from the authors. [37][38][39][40] In particular, besides the metallization, the often overlooked role played by the emitter stack (previously investigated only in a study by Anholt 22 ) has been analyzed in a state-of-the-art InGaP/GaAs HBTs in previous papers [38][39][40] ; the relevance of these studies is driven by the low thermal conductivities of the ternary InGaAs and InGaP emitter layers (even lower than GaAs), which make thermal shunt solutions less effective. For this purpose, the authors have used a simulation/modeling strategy based on combining (1) a tool that relies on a 3-D finite-element method (FEM) software package aided by an in-house routine, and (2) Design of Experiments (DOE) to analytically derive a predictive thermal resistance model starting from a minimized number of FEM results. Contrary to prior work, the proposed tool ensures very high simulation accuracy: starting from the actual masks used for device fabrication, it allows an automated and extremely detailed construction/meshing of the 3-D transistor structure in the environment of the FEM solver. Thanks to this feature, it can be easily integrated into a standard design process, and can in principle be used for any device technology.This work aims at extending the analysis presented in Catalano et al 38 where the impact of emitter stack and metallization layers on the thermal behavior was evaluated for various emitter areas and shapes in single-finger InGaP/GaAs HBTs. Compared wi...

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“…Flip‐chip technology1, introduced by IBM in 1964 and well‐known as C4 (Controlled Collapse Chip Connection), has been used so far mainly for computers and car electronics. Although C4 is the most widely recognised flip‐chip technology, other companies have developed other technologies and use them successfully 2345678. Today the variety of technologies is wide and the applications cover, besides computers and car electronics, areas like telecommunications, consumer electronics, LCDs, watches, PCMCIA cards, military and optoelectronics.…”

Section: Introductionmentioning

confidence: 99%

Precision Tin/Lead Alloy Plating for Flip‐Chip Mounting Technology

Richter

Ruess²,

Gemmler³

et al. 1997

Microelectronics International

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Bumping is a prerequisite for flip‐chip attachment of bare dies. For silicon semiconductors bumping is normally performed on the ICs at wafer scale. Bumping can be performed by micro‐plating or vacuum deposition techniques. Mechanical methods are also well known. In this paper a bumping process based on tin/lead alloy plating is reported. The plating bath presented enables the deposition of both solder compositions used for flip‐chip attachment, the eutectic and the lead‐rich. All key issues of the plating process covering plating equipment, electrolyte characteristics and plating process parameters are discussed. Methods of bump characterisation and quality assurance are reported as an important part of the bumping process. The deciding process parameters leading to high quality solder bumps are demonstrated.

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Bump heat sink technology - A novel assembly technology suitable for power HBTs

Cited by 18 publications

References 6 publications

Thermal analysis and design of peripheral adaption power cell for power amplifier

Thermal analysis and design of peripheral adaption power cell for power amplifier

Accurate and efficient analysis of the upward heat flow in InGaP/GaAs HBTs through an automated FEM‐based tool and Design of Experiments

Precision Tin/Lead Alloy Plating for Flip‐Chip Mounting Technology

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