Bulk silicon photonic wire for one-chip integrated optical interconnection

Ji, Ho-Chul; Ha, K. H.; Na, K. W.; Kim, S. G.; Joe, In-Sung; Shin, Dongjae; Lee, K. H.; Suh, Sungsoo; Bok, J. K.; You, Yong-Sang; Hyung, Yong Woo; Kim, S. S.; Park, Y. D.; Chung, Chilhee

doi:10.1109/group4.2010.5643414

Cited by 10 publications

(3 citation statements)

References 7 publications

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“…However, the resistance increase and its impact to the device speed have been insignificant as shown in the 25-Gbps lasers, modulators, and photodiodes successfully developed on the BS platform. Details on the Sionly BS devices can be found in the previous reports [13], [14], and this section focuses on the III/V-on-BS devices, which have been recently added to the BS device library after the DRAM integration. The operating wavelength band of the III/V-on-BS devices has been the O band.…”

Section: Performance Of Iii/v-on-bs Platformmentioning

confidence: 99%

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Shin

Byun

Shim

et al. 2022

J. Lightwave Technol.

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The CMOS industry has been expecting silicon photonics to provide photonic and electro-photonic integrated circuits based on the CMOS processes and infrastructures for scalability of incumbent technology evolutions and creation of novel technologies. However, the compatibility with the legacy CMOS has been compromised with the development convenience of early silicon photonics in that the specialty silicon-on-insulator substrates have been widely used as integration platforms. Since this specialty substrate may hinder the photonics integration with legacy volume products later, a legacy-friendly integration platform with a generic bulk-silicon substrate has been developed for better compatibility. This paper overviews the bulk-silicon photonics platform born for DRAM integration, upgraded with III/V-on-bulk-Si lasers, and transplanted to LiDAR applications requiring the virtuous cycle of cost and volume. The photonics integration with DRAM was to resolve the speed-capacity tradeoff in the DRAM interconnects, and technical feasibility as well as lessons learned from the integration attempt are reviewed. The bulk-silicon device performance approaches that of silicon-oninsulator devices with the thermal advantage of ~40-% lower thermal impedance and the optical disadvantage of ~0.4-dB/mm higher waveguide loss. In the LiDAR applications, detection performance up to ~20 m at 20 fps by a single-chip scanner integrating tunable laser, semiconductor optical amplifiers, and optical phased array are presented with future outlooks.

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Section: Performance Of Iii/v-on-bs Platformmentioning

confidence: 99%

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Shin

Byun

Shim

et al. 2022

J. Lightwave Technol.

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“…A basic set of the required photonic devices that must be integrated in the process is shown in Figure 7. Currently, device and process development has focused on either solid phase epitaxy (SPE) silicon waveguides [34,35] or deposited polycrystalline silicon waveguides [3]. Both approaches have yielded waveguide losses below 10 dB/cm.…”

Section: Drammentioning

confidence: 99%

Integration of silicon photonics into electronic processes

2013

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Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model, integration was accomplished on multi-project wafers that were shared by standard electronic customers without requiring in-foundry process changes. Simple die or wafer-level post-processing has enabled low-loss waveguides by the removal of the substrate within photonic regions. The custom-process model of the DRAM industry instead enabled optimization of the photonic device fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also demonstrated within this process [1]. The constraints of zero-change integration have limited achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS processes [2]. Custom polysilicon deposition and processing conditions available for DRAM integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required process features, device design guidelines and integration methodology tradeoffs will be presented. Relevant device metrics of area and energy efficiency as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe-art electronics processes. Applications of this research towards the implementation of a computer system utilizing photonic interconnect for core-to-memory communication will also be discussed.

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“…Previous demonstrations in a 180-nm memory process have yielded waveguides with a loss of 10.5 dB/cm [9]. In the other variant of this method, amorphous silicon is deposited over the deep trench and then crystallized using solid phase epitaxy [10]. The crystallized silicon is then selectively etched to form waveguides with losses as low as 3 dB/cm in standalone operation, but when combined with electronics, the waveguide loss rises to 20 dB/cm [11].…”

Section: Introductionmentioning

confidence: 99%

Subtractive Photonics in Bulk CMOS

Ives,

Sarkar,

Hajimiri

2023

IEEE J. Solid-State Circuits

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Subtractive photonics is presented as a method for implementing photonic waveguides into any bulk CMOS or electronics process. Metal and glass are patterned in the backend layers by the foundry to reveal suspended dielectric waveguides when the metal is etched away. This method requires a simple wet etch and provides waveguiding of light up to the visible regime using the broad transparency windows of silicon oxides. Mechanical, chemical, and photonic considerations are discussed, and photonic design is extensively detailed in the context of a 180-nm CMOS process. Example waveguides are constructed and measured, with losses as low as 4.1 dB/cm for a multimode waveguide at 1550 nm. In addition, waveguides are measured in the visible range, waveguide-photodiode couplers are detailed, and electronic-photonic systems are demonstrated to be unaffected by the etching.

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Bulk silicon photonic wire for one-chip integrated optical interconnection

Cited by 10 publications

References 7 publications

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Bulk-Si Platform: Born for DRAM, Upgraded With On-Chip Lasers, and Transplanted to LiDAR

Integration of silicon photonics into electronic processes

Subtractive Photonics in Bulk CMOS

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