Built-in self-test

Zorian, Y.

doi:10.1016/s0167-9317(99)00434-7

Cited by 7 publications

(2 citation statements)

References 5 publications

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“…Redundancy of components in an electronic device leads to fault tolerance. If, after the implementation of a BIST method, a defective component is detected, one strategy is to isolate this faulty component from the rest of the device and carry on device operation using the remaining functional components [ 90 ].…”

Section: Bist Methods Building On Multi-functional Sensorsmentioning

confidence: 99%

Built-In Self-Test (BIST) Methods for MEMS: A Review

2020

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A novel taxonomy of built-in self-test (BIST) methods is presented for the testing of micro-electro-mechanical systems (MEMS). With MEMS testing representing 50% of the total costs of the end product, BIST solutions that are cost-effective, non-intrusive and able to operate non-intrusively during system operation are being actively sought after. After an extensive review of the various testing methods, a classification table is provided that benchmarks such methods according to four performance metrics: ease of implementation, usefulness, test duration and power consumption. The performance table provides also the domain of application of the method that includes field test, power-on test or assembly phase test. Although BIST methods are application dependent, the use of the inherent multi-modal sensing capability of most sensors offers interesting prospects for effective BIST, as well as built-in self-repair (BISR).

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Section: Bist Methods Building On Multi-functional Sensorsmentioning

confidence: 99%

Built-In Self-Test (BIST) Methods for MEMS: A Review

2020

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“…BIST as a testing method for logic circuits has been widely used [3][4][5][6]. In last two decades different BIST architectures have been developed for FPGA testing; each of them has some pros and cons [7][8][9].…”

Section: -Introductionmentioning

confidence: 99%

BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs

Jahanirad

Karam

2018

ESJ

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FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST -based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.

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LUT Design with Automated Built-in Self-test Functionality

Karam

Jahanirad

2018

Lecture Notes in Electrical Engineering

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Built-in self-test

Cited by 7 publications

References 5 publications

Built-In Self-Test (BIST) Methods for MEMS: A Review

Built-In Self-Test (BIST) Methods for MEMS: A Review

BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs

LUT Design with Automated Built-in Self-test Functionality

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