Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation

Monnereau, Nicolas; Caignet, Fabrice; Trémouilles, David; Nolhier, Nicolas; Bafleur, Marise

doi:10.1016/j.microrel.2012.04.012

Cited by 15 publications

(31 citation statements)

References 5 publications

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“…Following previous works [3,5,9], behavioral models of the on-chip protection strategy are built using quasi-static measurements. We extract the quasistatic IV curves of the LIN components using a TLP generator with 100ns duration and 1ns rise time.…”

Section: Esd Protection Blockmentioning

confidence: 99%

“…By measuring those 3 pins, we are able to reconstruct (or reproduce the behavior) of the on-chip ESD protection strategy. This strategy is crucial to reproduce the on-chip current paths that can differ related to the off-chip components [3]. The Fig.2 shows the quasi-static IV curves of the LIN-GND protection under positive stress for the different LINs named A, B and C. It can be noticed that on these 3 components, the ESD strategy is different.…”

Section: Esd Protection Blockmentioning

confidence: 99%

“…All failures can be listed in two groups. The first one called "Hard failure" is the destruction of the IC, already mentioned in [3,4]. The second one is the "Soft Failure" [5,6,7,8] which relates to functional problems such as the lost of clock, RESET, etc… In this paper, we propose a methodology to develop a behavior model of the LIN component based on different set-up measurements.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Prediction of LIN communication robustness against EFT events using dedicated failure models

Escudié

Caignet

Nolhier

et al. 2017

Microelectronics Reliability

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To cite this version:Fabien Escudié, Fabrice Caignet, Nicolas Nolhier, Marise Bafleur. Prediction of LIN communication robustness against EFT events using dedicated failure models. Microelectronics Reliability, Elsevier, 2017, 76-77, pp.685 -691 AbstractDuring its life, an automotive application can encounter several perturbations such as fast transient of ESD discharges. In this paper, we propose a LIN transceiver behavior model to predict both hard and soft failures within a communication link. The proposed model, extracted from measurements, is implemented into simulation as a failure block. We will show that depending on the output state of the LIN, the data reading behavior could be different. Using such model, corrections at system level can be implemented to avoid failures.

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Section: Esd Protection Blockmentioning

confidence: 99%

Section: Esd Protection Blockmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Prediction of LIN communication robustness against EFT events using dedicated failure models

Escudié

Caignet

Nolhier

et al. 2017

Microelectronics Reliability

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“…The modeling of the system is based on previous work [14], [17], [18] and VHDL-AMS (Very-high-speed integrated circuit Hardware Description Language-Analog and Mixed Signals) is used as the description language [19]. The methodology is intended to model a system composed of digital ICs mounted on a Printed Circuit Board.…”

Section: A Modeling Of the Systemmentioning

confidence: 99%

“…In a previous paper [14] we have presented a methodology to build behavioral simulation of system-level ESD to study the propagation of an ESD into a system. In this paper, we applied and improved the methodology with behavioral ESD protection's structures, in order to both predict the susceptibility and try to extract a basic formulation of the failure probability.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

Monnereau

Caignet

Nolhier

et al. 2012

IEEE Trans. Device Mater. Relib.

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Due to growing number of embedded electronics, estimating failure related to system-level electrostatic discharge (ESD) consideration has become a major concern. In this paper, a behavioral modeling methodology to predict ESD failures at system level is proposed and validated. The proposed models enable time-domain simulation to determine the voltage and current waveforms inside and outside an integrated circuit during ESD events and then to predict the susceptibility of an electronic system to ESD. The purpose of this methodology is based on the improvement of Input/output Buffer Information Specification files widely used in signal integrity simulation. A simple case study is proposed to investigate the susceptibility of latch devices to transient stresses. Simulations and measurements are compared. Analytical formulations to determine the probability of susceptibility failure are proposed and compared with measurements.

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ESD Protection Methodologies

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Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation

Cited by 15 publications

References 5 publications

Prediction of LIN communication robustness against EFT events using dedicated failure models

Prediction of LIN communication robustness against EFT events using dedicated failure models

Investigation of Modeling System ESD Failure and Probability Using IBIS ESD Models

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