Building IEEE 802.15.4 Accelerators for Heterogeneous Wireless Sensor Nodes

Gomes, Tiago; Pinto, S.; Salgado, F.; Tavares, Adriano; Cabral, Jorge

doi:10.1109/lsens.2017.2681625

Cited by 12 publications

(7 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Connectivity and Interoperability issues are slowly being addressed in reconfigurable platforms by hardware-assisted solutions that can accelerate protocols and standards widely adopted at the network edge [90]. For instance, some communication activities related to data privacy (e.g., authentication, data encryption/decryption) are highly time-and battery-consuming.…”

Section: Rec-tandc #1 (Connectivity and Interoperability)mentioning

confidence: 99%

“…The architecture is deployed on an FPSoC platform (Microsemi SmartFusion2), which combines a hardcore MCU (Arm Cortex-M3) tightly-coupled to a Flash-based FPGA and an IEEE 802.15.4 radio transceiver externally attached. The offloaded hardware accelerators (e.g., SDP, cryptographic hardware blocks, network-related accelerators such as IEEE 802.15.4 [90], 6LoWPAN [91], and IPv6/UDP packet filtering) are available to the MCU as hardware peripherals and accessed by a standard on-chip communication protocol, which eases design and reduces access latency. The contribution from Vera-Salas et al [108] used a micropositioning measurement system to test and deploy their platform.…”

Section: Reconfigurable Platforms and Iot Motes: Putting It All Togethermentioning

confidence: 99%

See 1 more Smart Citation

The Future of Low-End Motes in the Internet of Things: A Prospective Paper

et al. 2020

View full text Add to dashboard Cite

Undeniably, the Internet of Things (IoT) ecosystem continues to evolve at a breakneck pace, exceeding all growth expectations and ubiquity barriers. From sensor to cloud, this giant network keeps breaking technological bounds in several domains, and wireless sensor nodes (motes) are expected to be predominant as the number of IoT devices grows towards the trillions. However, their future in the IoT ecosystem still seems foggy, where several challenges, such as (i) device’s connectivity, (ii) intelligence at the edge, (iii) security and privacy concerns, and (iv) growing energy needs, keep pulling in opposite directions. This prospective paper offers a succinct and forward-looking review of recent trends, challenges, and state-of-the-art solutions of low-end IoT motes, where reconfigurable computing technology plays a key role in tomorrow’s IoT devices.

show abstract

Section: Rec-tandc #1 (Connectivity and Interoperability)mentioning

confidence: 99%

Section: Reconfigurable Platforms and Iot Motes: Putting It All Togethermentioning

confidence: 99%

The Future of Low-End Motes in the Internet of Things: A Prospective Paper

et al. 2020

View full text Add to dashboard Cite

show abstract

“…The hardware part is used when high speed and parallel computation are required, while the software is employed to add more flexibility and connectivity to the designed system. The use of platforms based on SoC architecture have gained particular attention [18][19][20][21]. However, the existing platforms in [18,19] do not use FPGA as the hardware accelerator of computationally complex algorithms and those of [18][19][20][21] do not consider the HW/SW co-design to evaluate the energy/quality of the designed systems.…”

Section: Related Workmentioning

confidence: 99%

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

Jridi

Chapel

Dorez

et al. 2018

JLPEA

View full text Add to dashboard Cite

This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times.

show abstract

“…The simulation results are highlighted for IEEE 802.15.4 transmitter submodules. Gomes et al [20], [21] discuss the low-power wireless personal area network (6LoWPAN) accelerator module for IoT devices on the FPGA platform. The work analyzes PAN accelerator,  ISSN: 2088-8708 Int J Elec & Comp Eng, Vol.…”

Section: Introductionmentioning

confidence: 99%

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

Raj

Gowda

2022

IJECE

View full text Add to dashboard Cite

<span lang="EN-US">The IEEE 802.15.4 <a name="_Hlk109306810"></a>physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in wireless personal area network (WPAN) applications. In this paper, an efficient IEEE 802.15.4 digital transceiver hardware architecture is designed using the binary phase-shift keying (BPSK) technique. The transceiver mainly has transmitter and receiver modules along with the error calculation unit. The BPSK modulation and demodulation are designed using a digital frequency synthesizer (DFS). The DFS is used to generate the in-phase (I) and quadrature-phase (Q) signals and also provides better system performance than the conventional voltage-controlled oscillator (VCO) and look up table (LUT) based memory methods. The differential encoding-decoding mechanism is incorporated to recover the bits effectively and to reduce the hardware complexity. The simulation results are illustrated and used to find the error bits. The design utilizes less chip area, works at 268.2 MHz, and consumes 108 mW of total power. The IEEE 802.15.4 transceiver provides a latency of 3.5 clock cycles and works with a throughput of 76.62 Mbps. The bit error rate (BER) of 2×10-5 is achieved by the proposed digital transceiver and is suitable for real-time applications. The work is compared with existing similar approaches with better improvement in performance parameters.</span>

show abstract

Building IEEE 802.15.4 Accelerators for Heterogeneous Wireless Sensor Nodes

Cited by 12 publications

References 10 publications

The Future of Low-End Motes in the Internet of Things: A Prospective Paper

The Future of Low-End Motes in the Internet of Things: A Prospective Paper

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

Contact Info

Product

Resources

About