Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC

Protecting caches against multi-bit errors using embedded erasure coding

“…Moreover, the proposed technique is implemented in a reconfigurable way that depending on the desired level of performance/reliability, the reserved way in different parts (banks) of the cache can be considered as either erasure storage or normal data storage. In contrast to similar schemes [7,11,12], our proposed scheme does not require any significant change to the existing cache architecture of processors to add redundant rows.…”

“…In CPPC [11], two registers are added to the cache to store the XOR of all data written to the cache and all dirty data evicted from it, respectively. In [12], the proposed scheme extends SECDED to correct one more faulty bit using an erasure coding concept. Note that both 2D error coding [7] and CPPC [11] schemes incur a lot of area and power overhead due to over-design for correcting up to 8x8 clustered MBUs.…”

“…A variety of error-correction-codes (ECC) have been proposed to protect SRAM cache memories against soft errors [6][7][8][9][10][11][12]. However, the majority of existing MBU correction techniques are only able to correct a predefined number of errors per word.…”

Security enhancement of cloud servers with a redundancy-based fault-tolerant cache structure

“…In a conventional design, single-bit soft errors can be corrected by common ECC, such as SEC-DED codes [20,21] used in L2 caches of multiprocessors [22]. While CMPs with multiple L2 caches can cause more MBSEs [23], two adaptive ECC schemes have been used to enhance soft error tolerance of L1 and L2 cache [24]. They focus on the 345 impacts of soft errors in L1 and L2 caches on iterative sparse linear solvers, which can significantly reduce the soft error vulnerability in sparse linear solvers, and Several architectural techniques have also been proposed to improve reliability of on-chip cache by using either redundancy or cache resizing.…”