Building Custom FIR Filters Using System Generator

Hwang, J.C.M.; Ballagh, Jonathan

doi:10.1007/3-540-46117-5_117

Cited by 5 publications

(2 citation statements)

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“…A new filtering block, to be developed with System Generator tool from XILINX, is already foreseen. This will exploit the generation of FPGA code with the high level Simulink and MATLAB tools, which provide robust libraries for digital signal processing [22].…”

Section: Discussionmentioning

confidence: 99%

HDL based FPGA interface library for data acquisition and multipurpose real time algorithm processing

Fernandes¹,

Pereira²,

Sousa³

et al. 2010

2010 17th IEEE-NPSS Real Time Conference

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The inherent parallelism of the logic resources, the flexibility in its configuration and the performance at high processing frequencies makes the field programmable gate array (FPGA) the most suitable device to be used both for real time algorithm processing and data transfer in instrumentation modules. Moreover, the reconfigurability of these FPGA based modules enables exploiting different applications on the same module. When using a reconfigurable module for various applications, the availability of a common interface library for easier implementation of the algorithms on the FPGA leads to more efficient development. The FPGA configuration is usually specified in a hardware description language (HDL) or other higher level descriptive language. The critical paths, as the management of internal hardware clocks, that require deep knowledge of the module behavior shall be implemented in HDL to optimize the timing constraints. The common interface library should include these critical paths, freeing the application designer from hardware complexity and able to choose any of the available high-level abstraction languages for the algorithm implementation. With this purpose a modular Verilog code was developed for the Virtex 4 FPGA of the in-house Transient Recorder and Processor (TRP) hardware module, based on the Advanced Telecommunications Computing Architecture (ATCA), with eight channels sampling at up to 400 MSamples/s. The TRP was designed to perform real time Pulse Height Analysis (PHA), Pulse Shape Discrimination (PSD) and Pile-Up Rejection (PUR) algorithms at a high count rate (few MHz). A brief description of this modular code is presented and examples of its use as interface with end user algorithms, including a PHA with PUR, are described.

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Section: Discussionmentioning

confidence: 99%

HDL based FPGA interface library for data acquisition and multipurpose real time algorithm processing

Fernandes¹,

Pereira²,

Sousa³

et al. 2010

2010 17th IEEE-NPSS Real Time Conference

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“…To ease the burden of using the new functions and to meet system standards, FPGA vendors offered logic generators to build targeted functionality from a combination of their dedicated functions and soft logic [22]. Generators Trimberger: Three Ages of FPGAs and libraries of soft logic provided the interfaces to CoreConnect, AXI and other busses for peripherals on soft and hardened processors.…”

Section: Age Of Accumulation 2000-2007mentioning

confidence: 99%

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Trimberger

2015

Proc. IEEE

182

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Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore's Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed ''Ages'' in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.

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