Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System

Li, Songyuan; Meng, Jun; Yu, Licheng; Ma, Jianliang; Chen, Tianzhou; Wu, Minghui

doi:10.1109/hpcc-css-icess.2015.290

Cited by 6 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Heterogeneous systems are exponentially increasing their importance and diffusion 1 in both personal and industrial markets. Mobile, automotive, process management, sensor networks, health‐care, and IoT‐related domains are just a few examples witnessing this trend.…”

Section: Introductionmentioning

confidence: 99%

Flexible task‐DAG management in PHAST library: Data‐parallel tasks and orchestration support for heterogeneous systems

Peccerillo

Bartolini

2020

Concurrency and Computation

View full text Add to dashboard Cite

Summary Heterogeneous architectures proved successful in achieving unprecedented performance and energy‐efficiency. However, taking advantage of these diverse processing elements is still hard. Programmers need to code through the different approaches suitable for each target architecture and need to decide the distribution of activities on the different resources. The majority of current frameworks focuses on either performance or productivity. The former mainly provides low‐level target‐specific programming interfaces, and the latter offers high‐level tools that often fail in achieving high‐performance. In both cases, the design is usually data‐parallel, as task‐parallelism is not supported. In this work, we propose a task‐based solution within the data‐parallel heterogeneous single‐source PHAST library. Tasks can be coded in a target‐agnostic fashion, can be compiled and parallelized on multi‐core CPUs and NVIDIA GPUs automatically and support the choice of the execution platform at runtime. We evaluate the capabilities of the proposed task‐directed acyclic graph support in case of an extensive set of randomly generated task‐based applications with different sizes and characteristics. We compare it against a SYCL implementation in terms of performance and complexity metrics, highlighting that PHAST achieves about 1.56× and 2.60× speedup over SYCL for multi‐core CPU and GPU, respectively, while improving also code complexity metrics.

show abstract

Section: Introductionmentioning

confidence: 99%

Flexible task‐DAG management in PHAST library: Data‐parallel tasks and orchestration support for heterogeneous systems

Peccerillo

Bartolini

2020

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…This adaptive method is suitable for CMP processors where the prefetcher resides in the shared LCC. Li et al [4] and others used the GPU's memory delay tolerance feature to propose a buffer filter strategy for sharing LLC. This strategy adds a buffer filter to the memory.…”

mentioning

confidence: 99%

Miss-aware LLC buffer management strategy based on heterogeneous multi-core

et al. 2019

View full text Add to dashboard Cite

When multiple processor (CPU) cores and a GPU integrated together on the same chip share the last-level cache (LLC), the competition for LLC is more serious. CPU and GPU have different memory access characteristics, so that they have differences in the sensitivity of LLC capacity. For many CPU applications, a reduced share of the LLC could lead to significant performance degradation. On the contrary, GPU applications have high number of concurrent threads and they can tolerate access latency. Taking into account the GPU program memory latency tolerance characteristics, we propose an LLC buffer management strategy (buffer-for-GPU, BFG) for heterogeneous multi-core. A buffer is added on the side of LLC to filtrate streaming requests of GPU. Cache-insensitive GPU messages directly access to buffer instead of accessing to LLC, thereby filtering the GPU request and freeing up the LLC space for the CPU application. Then, for the different characteristics of CPU and GPU applications, an improved LRU replacement taking into account the recent access time and access frequency of the cache block is adopted. The cache missesaware algorithm dynamically selects the improved LRU or LRU algorithm to fit the current operating state by comparing the miss rate of cache in buffer so that the performance of the system will be improved significantly.

show abstract