Buck converter modeling in SystemVerilog for verification and virtual test applications

Verification Platform of 40Gbps High-speed Serial Interface Chip Based on UVM

“…Therefore, it is difficult to meet verification requirements by using traditional hardware description languages. This paper adopts the systemverilog-based [4] UVM as the basis to construct the verification platform. UVM provides abundant object-oriented class hierarchy structures, and introduces staged execution, callback, and report mechanisms which greatly simplify the construction of verification platform and improves the verification efficiency.…”