BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration

Franco, J.; Wu, Z.; Rzepa, G.; Vandooren, A.; Arimura, Hiroaki; Ragnarsson, Lars‐Åke; Hellings, Geert; Brus, S.; Cott, Daire; Heyn, V. De; Groeseneken, G.; Horiguchi, N.; Ryckaert, Julien; Collaert, N.; Linten, Dimitri; Kaczer, B.

doi:10.1109/iedm.2018.8614559

Cited by 19 publications

(16 citation statements)

References 3 publications

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“…Such BTI improvement exceeds the constant Eox scaling trend (dashed lines in Fig. 7) and confirms that the observed BTI improvements is mostly due to the high-k defect band decoupling with the insertion of LaSiOx or Al2O3 [14,27], where the defect energy shift can be estimated from the eWF modulation (~0.2eV for sample with 0.2nm Al2O3) in Fig. 6(a).…”

Section: B Evaluation Of Lasiox and Al2o3 Inserted Gate Stacks Onsupporting

confidence: 77%

“…2, with the insertion of 0.4nm LaSiOx, the PBTI reliability in low thermal budget processed gate stack (cf. w/ 0.4nm LaSiOx) shows clear improvement as compared to the reference: such improvement displays a steep slope at low EOT (where the SiO2 IL thickness is <5Å for the LaSiOx gate stack) and then follows the typical Eox scaling trend [14].…”

Section: A Demonstration Of Lasiox and Al2o3 Inserted Gate Stacks On ...mentioning

confidence: 84%

“…Early studies with rare-earth incorporated oxide have shown to improve the BTI reliability [10,11], following the demonstration of La-induced dipole in Ge nFET with improved PBTI reliability [12,13]. Recently, we have also showed LaSiOx and Al2O3inserted gate stacks on silicon MOS capacitors with improved BTI reliability [14,15,16]. In this work, the LaSiOx and Al2O3-inserted gate stacks are integrated into a planar transistor test vehicle, which enables a more extensive evaluation including channel carrier mobility and validates the gate stack integration in a complete device fabrication flow (including Beck-End-Of-Line processing), and further into a finFET test vehicle to demonstrate the compatibility with 3D device architectures.…”

Section: Introductionmentioning

confidence: 94%

“…To further explore the gate stack optimization space, SiO2 IL and high-k defect bands are calibrated with the BTI simulation framework "Comphy" based on the experimental data of the ref. stack without dipole-forming layers [14,23]. The impacts of SiO2 IL thickness and defect energy decoupling are studied: as shown in Fig.…”

Section: A Demonstration Of Lasiox and Al2o3 Inserted Gate Stacks On ...mentioning

confidence: 99%

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LaSiO_x- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

Franco

Vandooren

et al. 2022

IEEE Trans. Electron Devices

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Sequential 3D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high-k/metal gate (HKMG) stacks at reduced thermal budget (<525°C). The omission of the customary high-temperature gate stack anneal results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of "defect decoupling" layers -LaSiOx for nMOS, and Al2O3 for pMOSat the interface between SiO2 and HfO2 as a promising approach to engineer the high-k band lineup and minimize charge trapping for improved BTI reliability. In this paper, we demonstrate this approach in planar transistors, which allows also to assess the impact of defect decoupling on the carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving PBTI and NBTI reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate stack integration. Finally, the reliability improvement is validated also on a finFET test vehicle.

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Section: B Evaluation Of Lasiox and Al2o3 Inserted Gate Stacks Onsupporting

confidence: 77%

Section: A Demonstration Of Lasiox and Al2o3 Inserted Gate Stacks On ...mentioning

confidence: 84%

Section: Introductionmentioning

confidence: 94%

Section: A Demonstration Of Lasiox and Al2o3 Inserted Gate Stacks On ...mentioning

confidence: 99%

See 2 more Smart Citations

LaSiO_x- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

Franco

Vandooren

et al. 2022

IEEE Trans. Electron Devices

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“…Similar to the capacitor experiments reported in Section II, we fabricated two sets of transistors: the first one did not receive any high temperature step after metal deposition ('as deposited', which received only a sintering anneal at 400ºC in hydrogen; note: the lack of the so-called 'reliability anneal' is expected to yield severe BTI shifts [6,13]), while the second set received a 525ºC-2h PMA in nitrogen, intended to investigate the impact on BTI of the enhanced chemical interaction between the metals and the dielectric stack at higher thermal budgets. Note that the long PMA results in a shift of the lower effective work functions (eWF) towards midgap, as observed by the lowered pMOS Vth and increased nMOS Vth values in Fig.…”

Section: Experimental Results On Transistorsmentioning

confidence: 99%

On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI

Franco

Rzepa

et al. 2019

IEEE Trans. Device Mater. Relib.

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We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS Replacement Gate planar transistors with three selected work function metal stacks (representative of high-, standard, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework "Comphy", we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO2/HfO2 dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

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High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

Kim,

Ryu,

Nam

et al. 2024

Adv Funct Materials

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Direct printing of conjugated polymer thin‐film transistors enables the fabrication of deformable devices with low cost, high throughput, and large area. However, a relatively poor device performance of printed devices remains a major obstacle to their application in high‐end display backplanes and integrated circuits. In this study, high‐performance and highly stackable printed organic transistors is developed, arrays, and circuits using a near‐amorphous polymer, indacenodithiophene‐co‐benzothiadiazole (IDT‐BT). The printed devices exhibited high saturation mobility (>1 cm2 V−1 s−1), high on/off ratio (>107), and low subthreshold slope (245 mV dec−1). In addition, 16 × 16 printed IDT‐BT arrays achieved 100% fabrication yield, with excellent device‐to‐device uniformity and low variations of mobility (9.55%) and threshold voltage (4.51%), and good operational and environmental stability (>365 days). Furthermore, five stacked 3D transistors are demonstrated with an excellent 3D uniformity without compromising device performance due to a low required thermal budget for processing amorphous IDT‐BT. Finally, a new concept of 3D universal logic gate with high voltage gain (33.91 V/V) and record density (100 printed transistors per cm2) is proposed and fabricated, which is relevant for the commercialization of low‐cost printed display backplanes and high‐density integrated circuits based on highly processable polymeric semiconductors.

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BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration

Cited by 19 publications

References 3 publications

LaSiO_x- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

LaSiO_x- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI

High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

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BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration

Cited by 19 publications

References 3 publications

LaSiO x - and Al2O3-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

LaSiO x - and Al2O3-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI

High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

Contact Info

Product

Resources

About

LaSiO_x- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

LaSiO_x- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration