BTB-X: A Storage-Effective BTB Organization

Asheim, Truls; Grot, Boris; Kumar, Rakesh

doi:10.1109/lca.2021.3109945

Cited by 9 publications

(8 citation statements)

References 10 publications

(17 reference statements)

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“…Using these traces, we characterize BTB replacement challenges to design Thermometer, a novel profileguided BTB replacement technique. We validate Thermometer's effectiveness on 13 data center applications and on CBP-5 [15] and IPC-1 [17] traces that prior work [20,24,57,58] evaluate their frontend optimizations.…”

Section: Experimental Methodologymentioning

confidence: 99%

“…We profile only a portion of each application's execution; this portion is different from the tested execution and uses different inputs. Apart from evaluating Thermometer on these 13 real-world applications, we also evaluate Thermometer on a wide-range of common traces (663 CBP-5 [15] traces and 50 IPC-1 [17] traces) like prior work [20,24,57,58].…”

Section: Methodsmentioning

confidence: 99%

“…In addition to storing branch targets [87,110], BTB entries generally contain a tag and prediction information, while block-oriented BTBs also need to store the size of the corresponding basic block [148]. Existing work [24,32,40,65,81,110,118,128,132] proposes BTB compression techniques including using tags of fewer bits, removing page number, storing the branch target as a distance from the branch PC, or using a multilevel BTB. These techniques are orthogonal and can be combined with Thermometer to further improve the BTB storage efficiency.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Thermometer

Song

Khan

Shahri

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Modern processors employ a decoupled frontend with Fetch Directed Instruction Prefetching (FDIP) to avoid frontend stalls in data center applications. However, the large branch footprint of data center applications precipitates frequent Branch Target Buffer (BTB) misses that prohibit FDIP from eliminating more than 40% of all frontend stalls. We find that the state-of-the-art BTB optimization techniques (e.g., BTB prefetching and replacement mechanisms) cannot eliminate these misses due to their inadequate understanding of branch reuse behavior in data center applications.In this paper, we first perform a comprehensive characterization of the branch behavior of data center applications, and determine that identifying optimal BTB replacement decisions requires considering both transient and holistic (i.e., across the entire execution) branch behavior. We then present Thermometer, a novel BTB replacement technique that realizes the holistic branch behavior via a profile-guided analysis. Based on the collected profile, Thermometer generates useful BTB replacement hints that the underlying hardware can leverage. We evaluate Thermometer using 13 widelyused data center applications and demonstrate that it provides an average speedup of 8.7% (0.4%-64.9%) while outperforming the state-of-the-art BTB replacement techniques by 5.6× (on average, the best performing prior work achieves 1.5% speedup). We also demonstrate that Thermometer achieves a performance speedup that is, on average, 83.6% of the speedup achieved by the optimal BTB replacement policy.

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Section: Experimental Methodologymentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Thermometer

Song

Khan

Shahri

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…In addition to BTB prefetching, researchers have investigated BTB entry organizations to maximize the number of entries in a given storage budget [14,37,38].…”

Section: Related Workmentioning

confidence: 99%

Shooting Down the Server Front-End Bottleneck

Kumar

Grot

2020

ACM Trans. Comput. Syst.

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The front-end bottleneck is a well-established problem in server workloads owing to their deep software stacks and large instruction footprints. Despite years of research into effective L1-I and BTB prefetching, state-of-the-art techniques force a trade-off between metadata storage cost and performance. Temporal Stream prefetchers deliver high performance but require a prohibitive amount of metadata to accommodate the temporal history. Meanwhile, BTB-directed prefetchers incur low cost by using the existing in-core branch prediction structures but fall short on performance due to BTB’s inability to capture the massive control flow working set of server applications. This work overcomes the fundamental limitation of BTB-directed prefetchers, which is capturing a large control flow working set within an affordable BTB storage budget. We re-envision the BTB organization to maximize its control flow coverage by observing that an application’s instruction footprint can be mapped as a combination of its unconditional branch working set and, for each unconditional branch, a spatial encoding of the cache blocks around the branch target. Effectively capturing a map of the application’s instruction footprint in the BTB enables highly effective BTB-directed prefetching that outperforms the state-of-the-art prefetchers by up to 10% for equivalent storage budget.

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“…For example, certain BTB structures allocate different-sized target table entries to accommodate more branch instructions [8]. Asheim's experiments demonstrated that gradually expanding the BTB structure can significantly reduce mispredictions [9]. However, the increased BTB capacity introduces more access latency, resulting in longer branch instruction prediction times and increase power consumption.…”

Section: Introductionmentioning

confidence: 99%

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

Nian,

Liu,

Gao

et al. 2024

Electronics

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Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB’s capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency.

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BTB-X: A Storage-Effective BTB Organization

Cited by 9 publications

References 10 publications

Thermometer

Thermometer

Shooting Down the Server Front-End Bottleneck

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

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