BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion

Laleni

et al. 2023

Preprint

Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level FeFET cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variabil21 ity effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based ferroelectric field-effect transistor (FeFET) devices. Unlike tradi23 tional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6%accuracy for handwriting recognition and 91.5%accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achiev28 ing 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional struc31 tural overhead.

Section: Methods 1fefet-1r Cell Characterizationmentioning

confidence: 99%

mentioning

confidence: 99%

First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET

Soliman

Laleni

et al. 2023

Preprint

“…The FDSOI transistor is modeled using the industry-standard BSIM-IMG model [36], [37]. The effect of BG bias is automatically included in the BSIM model [38]. This allows us to perform BG read, where the inversion layer is actually formed at the Channel/BOX interface as shown in Fig.…”

Section: A Our Spice Modeling and Validation Of Fefetmentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

IEEE Trans. Circuits Syst. I

Thomann

et al. 2023

Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with > 10 larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET.We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a crosslayer manner is indispensable.

“…The transistor dimensions of the fabricated high-κ / metal gate FDSOI FET [3] used for compact model calibration are as: gate length = 20 nm, buried oxide (BOX) thickness (T box ) = 25 nm, and front gate oxide thickness = 1.1 nm. We have used the industry-standard BSIM-IMG compact model [12] to calibrate FDSOI FET. Fig.…”

Section: Transistor Model Calibration Withmentioning

confidence: 99%

Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing

Kumar

IEEE J. Explor. Solid-State Comput. Devices Circuits

Dabhi

et al. 2023

In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Depleted Silicon on Insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage (Vt) to be adjustable (i.e., low-Vt and high-Vt states) by using the back gate bias. Our design utilizes the front and back gates of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like; NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like; half adder and full adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates.