Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide

Stathis, James H.; LaRosa, G.; Chou, A.

doi:10.1109/relphy.2004.1315292

Cited by 23 publications

(6 citation statements)

References 16 publications

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“…This model can successfully explain the skew in C-V curve after the NBT stress [57], without assuming any unrealistic 1 : 1 correlation of interface traps and fixed charges. However, any localized (near the edges in energy band gap [58]) peak in trap generation while detected by I DLIN cannot be accounted for when CP data are corrected for the difference in ∆E, as done earlier, and would result in lower ∆V T estimation. Fig.…”

Section: B Measurement (Method Delay)-related Issuesmentioning

confidence: 99%

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

Mahapatra

Alam

2008

IEEE Trans. Device Mater. Relib.

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Section: B Measurement (Method Delay)-related Issuesmentioning

confidence: 99%

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

Mahapatra

Alam

2008

IEEE Trans. Device Mater. Relib.

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“…Once these differences are taken into account, the difference becomes much less than 20%. Finally, any non-uniform increased trap generation close to the conduction band edge [44] (beyond the charge pumping zone) can account for such small difference between corrected charge pumping and On-the-Fly I DLIN results.…”

Section: Si-o and Si-h Bondsmentioning

confidence: 96%

A comprehensive model for PMOS NBTI degradation: Recent progress

Alam

Kufluoglu

Varghese

et al. 2007

Microelectronics Reliability

277

159

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“…2 for accessing the density of process related and generated traps respectively before and after BTI stress. Note that direct characterization techniques such as Charge Pumping (CP) [6] and Gated Diode (or DCIV) [7] have been used in several reports to provide irrefutable proof of interface trap generation (ΔN IT ) for NBTI stress in SiON [5,[7][8][9][10][11][12][13][14][15] and HKMG [5,[16][17][18] p-MOSFETs. In spite of these experimental evidences, some reports have suggested hole trapping in pre-existing traps (ΔN HT ) as the only NBTI mechanism [19][20][21][22][23], which is definitely not correct.…”

Section: Introductionmentioning

confidence: 99%

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Mukhopadhyay

Mahapatra

2015

Fundamentals of Bias Temperature Instability in MOS Transistors

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In this chapter, direct characterization techniques have been used to access the trap generation and trapping subcomponents of BTI degradation in HKMG MOSFETs having different gate stack processes. Generation of new traps is estimated using DCIV for NBTI stress and both DCIV and SILC for PBTI stress respectively in p-and n-channel MOSFETs. Flicker noise is used to estimate the density of process related pre-existing gate insulator traps responsible for hole and electron trapping respectively during NBTI and PBTI stress. The spatial and energetic locations of generated traps for NBTI and PBTI stress are identified. The time, bias, and temperature dependencies of trap generation obtained using the DCIV technique are compared between NBTI and PBTI stress, while these parameters obtained using DCIV and SILC techniques are compared for PBTI stress. The relative dominance of trap generation and trapping on NBTI and PBTI threshold voltage degradation is estimated for different gate insulator processes. IntroductionFrom a practical point of view of technology qualification, it is important to know the magnitude of Bias Temperature Instability (BTI) at end-of-life of devices and hence of circuits and products under normal use condition. Estimation of Negative BTI (NBTI) and Positive BTI (PBTI) respectively in p-and n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is usually done by stressing the devices at higher than normal gate bias (V G = V G-STR ) and measuring the resulting device parametric degradation with minimal impact of recovery artifacts. Different "recovery-free" measurement techniques have been discussed in Chap. 2. As mentioned before, stress tests are usually performed for few hours or

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Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide

Cited by 23 publications

References 16 publications

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

A comprehensive model for PMOS NBTI degradation: Recent progress

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

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