Broad-band monolithic microwave active inductor and its application to miniaturized wide-band amplifiers

2006

This paper proposes a new multi-stage CMOS voltage-controlled ring VCO called modified Park-Kim ring VCO for multi-Gbps serial links. An in-depth comparative study of pros and cons of Park-Kim VCO and the modified Park-Kim VCO with both single and dual delay paths is given. We show that the modified Park-Kim VCO offers an improved oscillation frequency, large output voltage swing, comparable frequency tuning range and phase noise as compared with Park-Kim VCO proposed in [1,2]. We further show that although the modified Park-Kim VCO with single delay path and that with dual delay path offer comparable oscillation frequencies when the number of stages of the VCOs is high, the former provides a large frequency tuning range and reduced circuit complexity. To verify performance improvement, both Park-Kim VCOs and the modified ParkKim VCOs are implemented in TSMC's-0.18 µm, 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3 device models. Simulation results are presented.

Section: Modified Park-kim Vcosmentioning

confidence: 99%

A modified Park-Kim voltage-controlled ring oscillator for multi-Gbps serial links

2006

“…Gyrator-C active inductors are not chosen due to their high DC power consumption and the need for explicit DC biasing. Instead, the self-biased active inductors initially proposed for MESFETs [15] and later re-developed for CMOS [16,17], as shown in Fig. 1, are employed.…”

Section: Self-biased Active Inductormentioning

confidence: 99%

A Fully Differential VCO Cell with Active Inductors for Gbps Serial Links

2006

This paper investigates the distinct characteristics of cross-coupled fully differential ring VCO delay cells with resistor, current-source, and active inductor loads. In addition, it proposes a new cross-coupled fully differential ring VCO delay cell with self-biased active inductor load. The proposed VCO provides both rail-to-rail voltage swing and significantly increased oscillation frequency. Simulation results of 8-stage ring VCOs with various loads implemented in TSMC-0.18 µm 1.8 V 6-metal CMOS technology demonstrate that the delay of VCO cells with resistor load is much smaller than those with current-source load. The rise and fall times of the delay cell with self-biased active inductor are comparable to those with passive inductor load and are significantly smaller than those with resistor and current-source loads. VCOs with selfbiased active inductor and rail-to-rail swing provide rail-to-rail output voltage swing and comparable oscillation frequency as compared with those with self-biased active inductor load only. The frequency tuning range of VCOs with the active inductor load is smaller as compared with those with resistor/current-source load. The sensitivity of VCOs with active inductor load to supply voltage variation is comparable to that with passive inductor load, and is smaller than that with resistor/current-source load.

“…The transimpedance amplifier shown in in I [5] in I [4] in I [3] in I [2] in I [1] in D [5] D' [2] D' [3] D' [4] D tunable matching impedance to the channel. A Hara active inductor load proposed in [5] is employed to improve the bandwidth without using area-consuming spiral inductors.…”

Section: Transimpedance Amplifiersmentioning

confidence: 99%

A new parallel link interface with current-mode incremental signaling and per-pin skew compensation

2008

This paper proposes a new current-mode incremental signaling parallel link interface with per-pin skew compensation. Per-pin skew compensation is carried out in a calibration phase where clock-like training data are sent to all channels along with a reference clock of the same frequency. Training data are deskewed with respect to the common reference clock using DLLs such that all channels are skew-compensated simultaneously. New encoding and decoding scheme have been proposed to reduce the signal critical path at the transmitter. Transimpedance amplifiers with replica biasing are used to perform current-to-voltage conversion at the receiving end with a minimum sensitivity to supply voltage fluctuation. To evaluate the performance of the proposed skew compensating technique, a 1 Gbytes/s parallel link interface consisting of two data channels and one reference clock channel has been implemented with UMC 0.13 lm 1.2 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BIM3V3 device models. The channels are modeled as 50 X microstrip lines on a FR-4 substrate. Simulation results of the parallel link at all process corners have demonstrated that the proposed parallel link interface provides a minimum deskew range of 1.2 ns (±0.6 ns in each direction).