Bridging the programming gap between persistent and volatile memory using WrAP

Giles, Ellis; Doshi, Kshitij; Varman, Peter

doi:10.1145/2482767.2482806

Cited by 29 publications

(21 citation statements)

References 16 publications

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“…Persistent processor caches [17,36] and system-level persistence [25] would guarantee pending writes to NVM can be recovered after failures. It also eliminates the overhead of flushing caches for persistence [5].…”

Section: Related Workmentioning

confidence: 99%

Atomic In-place Updates for Non-volatile Main Memories with Kamino-Tx

Memaripour

Badam

Phanishayee

et al. 2017

Proceedings of the Twelfth European Conference on Computer Systems

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Data structures for non-volatile memories have to be designed such that they can be atomically modified using transactions. Existing atomicity methods require data to be copied in the critical path which significantly increases the latency of transactions. These overheads are further amplified for transactions on byte-addressable persistent memories where often the byte ranges modified for data structure updates are significantly smaller compared to the granularity at which data can be efficiently copied and logged. We propose Kamino-Tx that provides a new way to perform transactional updates on non-volatile byte-addressable memories (NVM) without requiring any copying of data in the critical path. Kamino-Tx maintains an additional copy of data off the critical path to achieve atomicity. But in doing so Kamino-Tx has to overcome two important challenges of safety and minimizing NVM storage overhead. We propose a more dynamic approach to maintaining the additional copy of data to reduce storage overheads. To further mitigate the storage overhead of using Kamino-Tx in a replicated setting, we develop Kamino-Tx-Chain, a variant of Chain Replication where replicas perform in-place updates and do not maintain data copies locally; replicas in Kamino-Tx-Chain leverage other replicas as copies to roll back or forward for atomicity. Our results show that using Kamino-Tx increases throughput by up to 9.5x for unreplicated systems and up to 2.2x for replicated settings.

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Section: Related Workmentioning

confidence: 99%

Atomic In-place Updates for Non-volatile Main Memories with Kamino-Tx

Memaripour

Badam

Phanishayee

et al. 2017

Proceedings of the Twelfth European Conference on Computer Systems

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“…Adding a small DRAM buffer in front of SCM to improve latency and to coalesce writes was proposed in [2]. The use of a volatile victim cache to prevent uncontrolled cache evictions from reaching SCM was described in [4]. However the controller in that work assumes sequential executions of wraps; it also required complicated comparison of victim cache and log data entries during pruning, and log searching to handle overflows.…”

Section: Related Workmentioning

confidence: 99%

“…Low-level memory scheduling to improve efficiency of persistent memory access was studied in [3]. Except for [4], none of these works deal with the issues of atomicity or durability of write sequences. Analysis of consistency models for persistent memory was considered in [6].…”

Section: Related Workmentioning

confidence: 99%

Non-Intrusive Persistence with a Backend NVM Controller

Doshi

Giles

et al. 2016

IEEE Comput. Arch. Lett.

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Abstract-By providing instruction-grained access to vast amounts of persistent data with ordinary loads and stores, byte-addressable storage class memory (SCM) has the potential to revolutionize system architecture. We describe a non-intrusive SCM controller for achieving light-weight failure atomicity through back-end operations. Our solution avoids costly software intervention by decoupling isolation and concurrency-driven atomicity from failure atomicity and durability, and does not require changes to the front-end cache hierarchy. Two implementation alternatives -one using a hardware structure, and the other extending memory controller with a firmware managed volatile space, are described.

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“…Flush of the log writes to SCM is done through bflush. Hardware support for committing transactions [12,24] would reduce the overhead of consistency.…”

Section: Infrastructure Servicesmentioning

confidence: 99%

Aerie

Volos

Nalli

Panneerselvam

et al. 2014

Proceedings of the Ninth European Conference on Computer Systems

118

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Storage-class memory technologies such as phase-change memory and memristors present a radically different interface to storage than existing block devices. As a result, they provide a unique opportunity to re-examine storage architectures. We find that the existing kernel-based stack of components, well suited for disks, unnecessarily limits the design and implementation of file systems for this new technology.We present Aerie, a flexible file-system architecture that exposes storage-class memory to user-mode programs so they can access files without kernel interaction. Aerie can implement a generic POSIX-like file system with performance similar to or better than a kernel implementation. The main benefit of Aerie, though, comes from enabling applications to optimize the file system interface. We demonstrate a specialized file system that reduces a hierarchical file system abstraction to a key/value store with fewer consistency guarantees but 20-109% higher performance than a kernel file system.

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Bridging the programming gap between persistent and volatile memory using WrAP

Cited by 29 publications

References 16 publications

Atomic In-place Updates for Non-volatile Main Memories with Kamino-Tx

Atomic In-place Updates for Non-volatile Main Memories with Kamino-Tx

Non-Intrusive Persistence with a Backend NVM Controller

Aerie

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