Bridging the gap between programming languages and hardware weak memory models

Abstract

We develop a new intermediate weak memory model, IMM, as a way of modularizing the proofs of correctness of compilation from concurrent programming languages with weak memory consistency semantics to mainstream multi-core architectures, such as POWER and ARM. We use IMM to prove the correctness of compilation from the promising semantics of Kang et al. to POWER (thereby correcting and improving their result) and ARMv7, as well as to the recently revised ARMv8 model. Our results are mechanized in Coq, and to the best of our knowledge, these are the first machine-verified compilation correctness results for models that are weaker than x86-TSO. Following the standard declarative (a.k.a. axiomatic) approach of defining memory consistency models [Alglave et al. 2014], the semantics of IMM programs is given in terms of execution graphs which partially order events. This is done in two steps. First, the program is mapped to a large set of execution graphs in which the read values are completely arbitrary. Then, this set is filtered by a consistency predicate, and only IMM-consistent execution graphs determine the possible outcomes of the program under IMM. Next, we define IMM's programming language ( §2.1), define IMM's execution graphs ( §2.2), and present the construction of execution graphs from programs ( §2.3). The next section ( §3) is devoted to present IMM's consistency predicate. 3 Recall that RMWs are relatively rare. The performance cost of this fixed compilation scheme is beyond the scope of this paper, and so is the improvement of the promising semantics to recover the correctness of the barrier-free compilation.

Grounding thin-air reads with event structures

“…As a result, PS cannot produce the outcome a = c = 1, which in turn means that its intended compilation to ARMv8 is unsound. To restore soundness of compilation from PS to ARMv8, Podkopaev et al [2019] insert a dmb.ld fence after every atomic update.…”

“…Proving the correctness of the intended optimal mappings from weakestmo to the full PowerPC model and to ARMv7, as well as to the ARMv8-Flat model [Pulte et al 2018], is left for future work. To carry out these proofs, we intend to compile via the recent IMM model of Podkopaev et al [2019], from which compilation results to multiple architectures have been developed.…”

“…defined the promising semantics, which comes with a number of results, which we are able to exploit for our weakest model. It has also led to some follow up work, which proved correctness of compilation to ARM [Podkopaev et al 2017[Podkopaev et al , 2019 and the correctness of a program logic over it [Svendsen et al 2018]. Nevertheless, as discussed, the promising semantics also has a number of shortcomings, which are difficult to resolve because of the model's complexity and brittleness.…”

Weakening WebAssembly

“…We have begun to see a new generation of models with the explicit aim of disallowing out-ofthin-air while preserving efficient compilation schemes Pichon-Pharabod and Sewell 2016;Podkopaev et al 2018]. As these models become more mature, it may be possible to use aspects of them to disallow our out-of-thin-air executions.…”

Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models

“…Understanding the details of these dependencies is not necessary for understanding the PARMv8 persistency semantics. We refer the reader to [Podkopaev et al 2019] for the details of how these dependencies are computed for a given program.…”