Bridged-Grain Solid-Phase-Crystallized Polycrystalline-Silicon Thin-Film Transistors

Zhou, Wei; Meng, Zhiguo; Zhao, Shuyun; Zhang, Meng; Chen, Rongsheng; Wong, Man; Kwok, Hoi‐Sing

doi:10.1109/led.2012.2210019

Cited by 42 publications

(40 citation statements)

References 18 publications

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“…Thin-Film Transistors technology [6]- [9] has been proposed and introduced to generate high-performance poly-Si TFTs. By selectively doping BG lines inside the active channel [6]- [9], grain size effect, shortchannel effect (SCE), and multijunction effect are beneficially exploited, resulting in excellent device electrical characteristics in terms of field-effect carrier mobility (μ FE ), threshold voltage (V th ), subthreshold swing (SS), and ON-current/OFFcurrent ratio (I ON /I OFF ).…”

Section: Characterization Of Dc-stress-induced Degradation In Bridgedmentioning

confidence: 99%

“…By selectively doping BG lines inside the active channel [6]- [9], grain size effect, shortchannel effect (SCE), and multijunction effect are beneficially exploited, resulting in excellent device electrical characteristics in terms of field-effect carrier mobility (μ FE ), threshold voltage (V th ), subthreshold swing (SS), and ON-current/OFFcurrent ratio (I ON /I OFF ). For these high-performance BG poly-Si TFTs, hitherto no systematical reliability studies have been performed and reported.…”

Section: Characterization Of Dc-stress-induced Degradation In Bridgedmentioning

confidence: 99%

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Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Zhang

Zhou

Chen

et al. 2014

IEEE Trans. Electron Devices

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In this paper, dc-stress-induced degradation in bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is systemically characterized and investigated. Compared with normal poly-Si TFTs, BG poly-Si TFTs exhibit better hot-carrier (HC) reliability, better self-heating (SH) reliability, and better negative bias temperature (NBT) instability. Resulting from the heavily doped BG lines inside the active channel, lateral electric field reduction at the drain side, Joule heat diffusion enhancement at the channel length direction, and boron-hydrogen bond formation at interface/grain boundaries are, respectively, responsible for the improved HC reliability, SH reliability, and NBT reliability in BG poly-Si TFTs. In addition, stress V g -dependent HC degradation with fixed stress V d , stress power density-dependent SH degradation, and vertical electrical field-dependent NBT degradation are also examined in both normal poly-Si TFTs and BG poly-Si TFTs. All test results indicate that such high-performance and highly reliable BG poly-Si TFT has a great potential for system-on-panel application.Index Terms-Bridged grain (BG), hot carrier (HC), negative bias temperature instability (NBTI), polycrystalline silicon (poly-Si), self-heating (SH), thin-film transistors (TFTs).

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Section: Characterization Of Dc-stress-induced Degradation In Bridgedmentioning

confidence: 99%

Section: Characterization Of Dc-stress-induced Degradation In Bridgedmentioning

confidence: 99%

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Zhang

Zhou

Chen

et al. 2014

IEEE Trans. Electron Devices

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“…Thus, previously, low-temperature polycrystalline silicon (poly-Si) was able to be used rather than a-Si:H in AMOLED. Three main low-temperature crystallization techniques are currently used: (1) solid-phase crystallization (SPC) [3], (2) metal-induced lateral crystallization (MILC) [4], and (3) excimer laser annealing (ELA) [5]. Although the SPC is the simplest technology among the other crystallization techniques, it needs to be performed by annealing at 600°C for 24 h, which results in a poor throughput for mass production.…”

Section: Introductionmentioning

confidence: 99%

Progress of p-channel bottom-gate poly-Si thin-film transistor by nickel silicide seed-induced lateral crystallization

et al. 2016

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Excimer laser annealing (ELA) is known to be the most common crystallization technology for the fabrication of low-temperature polycrystalline-silicon (poly-Si) thinfilm transistors (TFTs) in the mass production industry. This technology, however, cannot be applied to bottom-gate (BG) TFTs, which are well developed for the liquid-crystal display (LCD) back-planes, because strong laser energy of ELA can seriously damage the other layers. Here, we propose a novel high-performance BG poly-Si TFT using Ni silicide seed-induced lateral crystallization (SILC). The SILC technology renders it possible to ensure low damage in the layers, smooth surface, and longitudinal large grains in the channel. It was observed that the electrical properties exhibited a steep subthreshold slope of 110 mV/dec, high field-effect mobility of 304 cm 2 /Vsec, high I on /I off ratio of 5.9 9 10 7 , and a low threshold voltage of -3.9 V.

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“…A detailed discussion of the processing steps was provided elsewhere [1][2] 11 , the surface potential extracted from sub-threshold I-V curves is shown in Fig. 1(b).…”

Section: Devices Parameters and I-v Characteristicsmentioning

confidence: 99%

Analysis of low frequency noise characteristics inp-type polycrystalline silicon thin film transistors

Liu

Fang

2017

Mod. Phys. Lett. B

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Low frequency noises in the p-type polycrystalline silicon thin film transistors are investigated. It shows a pure 1/f γ (with γ near one) noise behavior which can be explained by emission and trapping processes of carriers between trapping states. Subsequently, the gate voltage-dependent drain current noise power spectral densities closely follow the mobility fluctuation model, and the average Hooge's parameter is then extracted. By considering traditional tunneling processes, the flat-band voltage spectral density is extracted and the concentration of traps in the grain boundary is calculated to be 7.17×10 20 cm −3 eV −1 . By converting the frequency to tunneling depth of carriers in the gate oxide, the spatial distribution of gate oxide trapped charges are obtained. Finally, the distribution of localized states in the energy band is extracted. The experimental results show an exponential deep states and tail states distribution in the band gap while N DD is about 1.5 × 10 20 cm −3 eV −1 , T DD is ∼ 617 K, N TD is ∼ 3.6 × 10 21 cm −3 eV −1 and T TD is ∼ 265 K.

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Bridged-Grain Solid-Phase-Crystallized Polycrystalline-Silicon Thin-Film Transistors

Cited by 42 publications

References 18 publications

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Progress of p-channel bottom-gate poly-Si thin-film transistor by nickel silicide seed-induced lateral crystallization

Analysis of low frequency noise characteristics inp-type polycrystalline silicon thin film transistors

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