Breakthrough of on-resistance Si limit by Super 3D MOSFET under 100V breakdown voltage

Yamaguchi, Hitoshi; Sakakibara, Jun; Urakami, Yasushi

doi:10.1109/ispsd.2007.4294913

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…The parameters that were used for the single-EPI, double-EPIs, and triple-EPIs structure simulation. Figure 12 compares the specific on-resistance performance of our proposed SGT devices with that of the other middle-voltage devices reported in [4,15,21,[32][33][34][35][36][37][38][39][40], ideal silicon limit, and super junction (SJ) limit for cell pitch = 5 and 10 µm in the 50-200 V range. Form Figure 12, we observe that the triple-EPIs structure and those using a double split-gate device [15] and stepped oxide SGTs [18,20,21] can achieve a very low R on,sp in the middle-voltage range because they all can maintain more uniform EF distributions between two trenches.…”

Section: Devicementioning

confidence: 99%

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

et al. 2020

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A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

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Section: Devicementioning

confidence: 99%

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

et al. 2020

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“…Efforts to extend the superjunction concept to lower voltage ranges (V bd < 100 V) use high-energy implantations [5], or very deep trench gates, in excess of 30 μm [6]. Such approaches strongly limit the suitability of superjunctions for smart power integration.…”

Section: Introductionmentioning

confidence: 99%

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

Moens

Roig

Desoete

et al. 2009

IEEE Trans. Device Mater. Relib.

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This paper discusses the hot-carrier and electrical safe operating area (SOA) of trench-based integrated power devices. The hot-carrier SOA is determined by the avalanche current, exhibiting a maximum at intermediate drain voltage. The initial hot-carrier degradation is dependent on the crystal plane on which the gate oxide is grown. During hot-carrier stress, interface states are formed in the device's accumulation region. No channel degradation is observed. The electrical SOA of the trench-based MOS (TB-MOS) is much larger than a comparable lateral DMOS (LDMOS) or vertical DMOS (VDMOS). Even for 100-ns pulses, the TB-MOS exhibits electrothermal effects, contrary to LDMOSand VDMOS. Finally, the intrinsic gate oxide quality of the trench gate oxide is reported on. It is proven that the oxide timedependent dielectric breakdown is determined by the thinnest oxide along the trench sidewall.

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Breakthrough of on-resistance Si limit by Super 3D MOSFET under 100V breakdown voltage

Cited by 2 publications

References 8 publications

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

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