Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Abstract

Based on the theoretical and experimental investigation of a thin silicon layer (TSL) with linear variable doping (LVD) and further research on the TSL LVD with a multiple step field plate (MSFP), a breakdown voltage (BV) model is proposed and experimentally verified in this paper. With the two-dimensional Poisson equation of the silicon on insulator (SOI) device, the lateral electric field in drift region of the thin silicon layer is assumed to be constant. For the SOI device with LVD in the thin silicon layer, the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field (ENDIF), from which the reduced surface field (RESURF) condition is deduced. The drain in the centre of the device has a good self-isolation effect, but the problem of the high voltage interconnection (HVI) line will become serious. The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device. Based on this model, the TSL LVD SOI n-channel lateral double-diffused MOSFET (nLDMOS) with MSFP is realized. The experimental breakdown voltage (BV) and specific on-resistance (Ron,sp) of the TSL LVD SOI device are 694 V and 21.3 Ω-mm2 with a drift region length of 60 μm, buried oxide layer of 3 μm, and silicon layer of 0.15 μm, respectively.

Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique

“…The critical electric field is a useful parameter for identifying the onset of avalanche breakdown within a device. 26) For SOI RESURF devices, the lateral breakdown voltage is determined by the two electric field peaks at the N-drift/N + -drain and P-well/N-drift junctions. When one of the two electric field peaks reaches the critical electric field, the lateral breakdown occurs.…”

Analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region

“…For RESURF devices, the avalanche breakdown occurs at the location with the maximum electric field. A useful parameter to identify the onset of avalanche breakdown within the device is the critical electric field; [21] when the maximum electric field in the device exceeds the critical electric field, the device breaks down. For the case that the drift region is completely-depleted, the electric field peaks are at the surfaces of the P-well/N-drift and N-drift/N + -drain junctions and at the interface of drift/substrate under the drain.…”

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

“…Owing to its ideal dielectric isolation, higher speed, less parasitic effect, and higher integration, silicon-on-insulator (SOI) technology is of great benefit to high voltage lateral double-diffusion metal-oxide-semiconductor (LDMOS) devices and has been widely developed for a variety of power ICs , such as automotive driver IC, display driver IC, highvoltage switching IC, LED driver IC, etc. [1][2][3][4][5][6][7] One of the main issues when designing LDMOS is the trade-off between breakdown voltage (BV) and specific on-resistance (R on,sp ). [8][9][10][11][12][13][14] Triple reduced surface field (RESURF) technology [15][16][17][18][19][20][21] is an excellent method in mass manufacture to achieve the tradeoff between BV and R on,sp .…”