Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques

Pyne, Sumanta; Pal, Ajit

doi:10.1166/jolpe.2012.1219

Cited by 1 publication

(1 citation statement)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To compare the area of the proposed schemes, we analyzed the area of the BTB schemes. In the conventional BTB structure [30,31], each table entry is approximately 56 bits, including the target index, target instruction address, and instruction type. The first level incorporates a fully associative register with 64 table entries in the two-level structure, and the second follows the conventional BTB structure.…”

Section: Analysis Of Areamentioning

confidence: 99%

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

Nian,

Liu,

Gao

et al. 2024

Electronics

View full text Add to dashboard Cite

Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB’s capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency.

show abstract

Section: Analysis Of Areamentioning

confidence: 99%