Branch Prediction Topologies for SMT Architectures

Pizzol, Guilherme Dal; Navaux, Philippe; Pilla, Maurı́cio L.

doi:10.1109/cahpc.2005.16

“…Several papers examine branch prediction on simultaneous multithreading processors [14,29]. In general, branch prediction was not shown to be a significant problem for that architecture, despite sharing of a single physical branch predictor.…”

Section: Other Related Workmentioning

confidence: 98%

Accurate branch prediction for short threads

Choi

¹

,

Porter

²

,

Tullsen

³

2008

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Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose parallelism. Current branch predictors seek to incorporate large amounts of control flow history to maximize accuracy. However, when that history is absent the predictor fails to work as intended. Thus, modern predictors are almost useless for threads below a certain length.Using a Speculative Multithreaded (SpMT) architecture as an example of a system which generates shorter threads, this work examines techniques to improve branch prediction accuracy when a new thread begins to execute on a different core. This paper proposes a minor change to the branch predictor that gives virtually the same performance on short threads as an idealized predictor that incorporates unknowable pre-history of a spawned speculative thread. At the same time, strong performance on long threads is preserved. The proposed technique sets the global history register of the spawned thread to the initial value of the program counter. This novel and simple design reduces branch mispredicts by 29% and provides as much as a 13% IPC improvement on selected SPEC2000 benchmarks.

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Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

Wang

¹

,

Hu

²

,

Ziavras

³

2012

IET Comput. Digit. Tech.

1

0

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Accurate branch prediction for short threads

Choi

¹

,

Porter

²

,

Tullsen

³

2008

Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems

15

0

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Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose parallelism. Current branch predictors seek to incorporate large amounts of control flow history to maximize accuracy. However, when that history is absent the predictor fails to work as intended. Thus, modern predictors are almost useless for threads below a certain length.Using a Speculative Multithreaded (SpMT) architecture as an example of a system which generates shorter threads, this work examines techniques to improve branch prediction accuracy when a new thread begins to execute on a different core. This paper proposes a minor change to the branch predictor that gives virtually the same performance on short threads as an idealized predictor that incorporates unknowable pre-history of a spawned speculative thread. At the same time, strong performance on long threads is preserved. The proposed technique sets the global history register of the spawned thread to the initial value of the program counter. This novel and simple design reduces branch mispredicts by 29% and provides as much as a 13% IPC improvement on selected SPEC2000 benchmarks.

show abstract

Branch Prediction Topologies for SMT Architectures

Cited by 6 publications

References 12 publications

Accurate branch prediction for short threads

Accurate branch prediction for short threads

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

Accurate branch prediction for short threads

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