Abstract:SUMMARYModern superscalar processors highly depend on e cient branch prediction to exploit a large amount of instruction level parallelism. However, it is known that branch prediction accuracy is degraded when process switches are present. At the same time, multithreading architectures are considered a good approach to increase the total throughput. In multithreading architectures, however, the process switch rate is very high and even a second level cache miss causes a process switch. In such an environment, … Show more
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