BOW: Breathing Operand Windows to Exploit Bypassing in GPUs

Esfeden, Hodjat Asghari; Abdolrashidi, AmirAli; Rahman, Shafiur; Wong, Daniel; Abu-Ghazaleh, Nael

doi:10.1109/micro50266.2020.00084

Cited by 10 publications

(4 citation statements)

References 50 publications

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“…In this section, we analyze the benefits and overheads of Malekeh and compare it with BOW [3] which has a sliding window of three instructions.…”

Section: Discussionmentioning

confidence: 99%

“…The model includes the arbiter, crossbar, RF banks, and CCUs. We compare our work against BOW [3], a state-of-the-art proposal for RF caching in GPUs. BOW replaces OCUs with buffers that keep the source operand values of instructions in a sliding window.…”

Section: Methodsmentioning

confidence: 99%

“…Asghari Esfeden et al [3] proposed a forwarding operand mechanism implemented in the OCUs. A detailed comparison between Malakeh and this work is presented in section 9.…”

Section: Related Workmentioning

confidence: 99%

“…Previous works have proposed caching mechanisms to reduce the energy consumption of the RF in GPUs [3][4][5]11]. An RF cache is smaller than the RF banks and is closer to the consumer pipelines.…”

Section: Introductionmentioning

confidence: 99%

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Lightweight Register File Caching in Collector Units for GPUs

Abaie Shoushtary,

Arnau,

Tubella Murgadas

et al. 2023

Proceedings of the 15th Workshop on General Purpose Processing Using GPU

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Modern GPUs benefit from a sizable Register File (RF) to provide fine-grained thread switching. As the RF is huge and accessed frequently, it consumes a considerable share of the dynamic energy of the GPU. Designing a large, high-throughput RF with low energy consumption and area for GPUs is challenging. In this paper, an energy-efficient hierarchical RF design for GPUs, called Malekeh, is introduced. Malekeh keeps registers in energy-efficient small caches and maximizes cache efficacy by using lightweight policies and supporting adaptive algorithms. The policies' effectiveness is improved by leveraging register reuse distance information provided by the compiler as a hint. Malekeh reduces the RF reads by 48.5% and dynamic energy by 29.1%. It also improves performance by 9.6% with a negligible overhead of 0.04% in area. CCS CONCEPTS• Computer systems organization → Parallel architectures.

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“…In this section, we analyze the benefits and overheads of Malekeh and compare it with BOW [3] which has a sliding window of three instructions.…”

Section: Discussionmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

“…Asghari Esfeden et al [3] proposed a forwarding operand mechanism implemented in the OCUs. A detailed comparison between Malakeh and this work is presented in section 9.…”

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Lightweight Register File Caching in Collector Units for GPUs

Abaie Shoushtary,

Arnau,

Tubella Murgadas

et al. 2023

Proceedings of the 15th Workshop on General Purpose Processing Using GPU

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Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures

Jiang

Kim

2021

Microprocessors and Microsystems

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TEA-RC: Thread Context-Aware Register Cache for GPUs

Jeong

et al. 2022

IEEE Access

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Graphics processing units (GPUs) achieve high throughput by exploiting a high degree of thread-level parallelism (TLP). To support such high TLP, GPUs have a large-sized register file to store the context of all threads, consuming around 20% of total GPU energy. Several previous studies have attempted to minimize the energy consumption of the register file by implementing an emerging non-volatile memory (NVM), leveraging its higher density and lower leakage power over SRAMs. To amortize the cost of long access latency of NVM, prior work adopts a hierarchical register file consisting of an SRAM-based register cache and an NVM-based registers where the register cache works as a write buffer. To get the register cache index, they use the partially selected bits of warp ID and register ID. This work observes that such an index calculation causes three types of contentions leading to the underutilization of the register cache: inter-warp, intra-warp, and false contentions. To minimize such contentions, this paper proposes a thread contextaware register cache (TEA-RC) in GPUs. In TEA-RC, the cache index is calculated considering the high correlation between the number of scheduled threads and the register usage of threads. The proposed design shows 28.5% higher performance and 9.1 percentage point lower energy consumption over the conventional register cache that concatenates three bits of warp ID and five bits of register ID to compute the cache index.INDEX TERMS Graphics processing units; register file; register cache; volatile memory; non-volatile memory, hybrid register file, hierarchical register file This article has been accepted for publication in IEEE Access.

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BOW: Breathing Operand Windows to Exploit Bypassing in GPUs

Cited by 10 publications

References 50 publications

Lightweight Register File Caching in Collector Units for GPUs

Lightweight Register File Caching in Collector Units for GPUs

Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures

TEA-RC: Thread Context-Aware Register Cache for GPUs

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