Bounded satisfiability checking of metric temporal logic specifications

Abstract

We introduce bounded satisfiability checking, a verification technique that extends bounded model checking by allowing also the analysis of a descriptive model, consisting of temporal logic formulae, instead of the more customary operational model, consisting of a state transition system. We define techniques for encoding temporal logic formulae into Boolean logic that support the use of bi-infinite time domain and of metric time operators. In the framework of bounded satisfiability checking, we show how a descriptive model can be refined into an operational one, and how the correctness of such a refinement can be verified for the bounded case, setting the stage for a stepwise system development method based on a bounded model refinement. Finally, we show how the adoption of a modular approach can make the bounded refinement process more manageable and efficient. All introduced concepts are extensively applied to a set of case studies, and thoroughly experimented through Zot, our SAT solver-based verification toolset.

How bit-vector logic can help improve the verification of LTL specifications over infinite domains

“…In the case of CLTLoc, the model built by hand is a standard timed lamp which has been used many times for testing the performance of verification tools (see, e.g., [21]), and which has been given a CLTLoc description in [9]. The bulk of the CLTLoc experiments, however, used models that have been created using the transformation from continuous-time MITL specifications that has been defined in [8,11].…”

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“…8) from [28]. The lamp is controlled by two buttons, labeled ON and OFF respectively, which cannot be pressed simultaneously.…”

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