Boosting mobile GPU performance with a decoupled access/execute fragment processor

Abstract

Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the operating time per battery charge. The CPU/GPU component is only left with a shrinking fraction of the power budget, since most of the energy is consumed by the screen and the antenna. In this paper, we focus on improving the energy efficiency of the GPU since graphical applications consist an important part of the existing market. Moreover, the trend towards better screens will inevitably lead to a higher demand for improved graphics rendering. We show that the main bottleneck for these applications is the texture cache and that traditional techniques for hiding memory latency (prefetching, multithreading) do not work well or come at a high energy cost. We thus propose the migration of GPU designs towards the decoupled access-execute concept. Furthermore, we significantly reduce bandwidth usage in the decoupled architecture by exploiting inter-core data sharing. Using commercial Android applications, we show that the end design can achieve 93% of the performance of a heavily multithreaded GPU while providing energy savings of 34%.

Efficient execution of memory access phases using dataflow specialization

“…Based on the outcome of the computation, a new set of events are created in parallel and arrive at the event block 4 . The event block applies boolean algebra on the events (as configured for that region with Event-Condition-Action (ECA) rules) to generate any actions which are delivered as action indices to the action block 5 . The action block takes the indices, selects the ones that could be issued in the current cycle, and controls the data bus to move the data values to the accelerator or between event queues 6 7 .…”

Efficient execution of memory access phases using dataflow specialization

“…Based on the outcome of the computation, a new set of events are created in parallel and arrive at the event block 4 . The event block applies boolean algebra on the events (as configured for that region with Event-Condition-Action (ECA) rules) to generate any actions which are delivered as action indices to the action block 5 . The action block takes the indices, selects the ones that could be issued in the current cycle, and controls the data bus to move the data values to the accelerator or between event queues 6 7 .…”

“…We combine the power of fetch, decode, dispatch, issue, RF and bypass logic as the red bar and show the functional unit power and load-store unit power separately 5 . Within MAD2, the computation block's power is 639 mW (closely matching and slightly less than FU power of OOO2), with the rest consuming 112 mW; the LSU is 800 mW.…”

“…Decoupled access-execute The classic DAE model was introduced in the early 1980s [62,31], and is incarnated in classic vector processors, conditional vectors, and the more recent VT and Maven architectures which are decoupled vector clustered microarchitectures [41,8] and in very recent work, in a fragment processor design [5] allowing/exploiting extremely regular addresses in graphics workloads. In a sense, accelerators can be viewed as vector cores with arbitrary vector chaining.…”

Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors

“…Decoupled Execution: Recently, there has been renewed interest in decoupled execution for improving performance in GPUs and manycore [6,1]. Decoupled execution leverages the compiler to partition a single thread of execution into separate memory-accessing and memory-consuming instruction streams called strands, which communicate data and control flow decisions with one another through FIFO data queues [22].…”