Boolean matching for full-custom ECL gates

Mayo, R.N.; Touati, H.

doi:10.1109/iccad.1993.580100

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

DOI: 10.1109/iccad.1993.580100

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Boolean matching for full-custom ECL gates

R.N. Mayo¹,

H. Touati²

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Recursive layout generation

Monier¹,

Haddad²,

Dion³

Proceedings Sixteenth Conference on Advanced Research in VLSI

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We present a recursive method for generating layout for V u 1 chips based on integrating layout directives in the netlist description. The method allows seamless integration of handdrawn and synthesized layout, so that hand layout need only be used where the increase in density is justified. Layout is generated automatically with predictable results; small changes in the source result in small changes of the overall layout. The system is versatile enough to build dense vu1 microprocessor chips automatically.

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Recursive layout generation

Monier¹,

Haddad²,

Dion³

Proceedings Sixteenth Conference on Advanced Research in VLSI

View full text Add to dashboard Cite

show abstract

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Boolean matching for full-custom ECL gates

Cited by 1 publication

References 5 publications

Recursive layout generation

Recursive layout generation

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