Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra

Gupta, Utkarsh; Kalla, Priyank; Rao, Vikas

doi:10.1109/tcad.2018.2818726

Cited by 7 publications

(21 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this section, we present a faster reduction algorithm for verifying GF arithmetic circuits more efficiently. Our reduction method uses the ZDD representation for a Boolean polynomial ring, as described in Section II, similar to the conventional best method [11]. The major difference is that the proposed method computes the Boolean polynomials of wires from primary inputs (PIs) to POs, whereas the conventional best method obtains them from POs to PIs.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…A formal verification method for gate-level netlists with functions given over the GF arithmetic was presented in 2019 [11]. The proposed method verified the circuit functions algebraically using ideal membership problems without any reference circuit.…”

Section: Formal Verification Of Circuit Netlists Over Gf Arithmeticmentioning

confidence: 99%

“…The circuit function was verified by checking whether the GF equation of a design specification could be derived from simultaneous GF equations expressing a gatelevel netlist. We briefly describe the method proposed by [11] in this section because it is currently the fastest and most efficient method to verify gate-level circuit netlists over GF arithmetic and is also closely related to our method.…”

Section: Formal Verification Of Circuit Netlists Over Gf Arithmeticmentioning

confidence: 99%

“…The other method involves the utilization of a Gröbner basis reduction [11]- [13]. This method performs circuit verification by examining whether a specification in the form of an F 2 polynomial can be derived from F 2 simultaneous algebraic equations extracted from a netlist.…”

Section: Introductionmentioning

confidence: 99%

“…The Gröbner basis reduction is employed to solve this problem (i.e., the ideal membership problem). Recently, because both (i) deriving the Gröbner basis and (ii) the following Gröbner basis reduction can be extremely time-consuming, [5], [11] developed a method in which the former could be omitted using the reverse topological term order (RTTO) and the latter can be performed faster by applying a zero-suppressed binary DD (ZDD) to represent polynomials over F 2 . However, when using the ZDD-based method, the possibility that the number of terms in the polynomials for intermediate nodes (i.e., the outputs of gates) would explode during the ZDD generation process still exists.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials

Ito

Ueno

Homma

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

In this study, we present a new formal method for verifying the functionality of Galois-field (GF) arithmetic circuits. Assuming that the input-output relation (i.e., the specification of a GF arithmetic circuit) can be represented as polynomials over F2, the proposed method formally checks the equivalence between GF polynomials derived from a netlist and the specification. To efficiently verify the equivalence, we employ a zero-suppressed binary decision diagram (ZDD) to represent polynomials over F2. Even though polynomial reduction is the most time-consuming process of verification (i.e., equivalence checking), our new algorithm can efficiently reduce the GF polynomials in the form of a zero-suppressed binary decision diagram derived from the target netlist. The proposed algorithm derives the polynomials representing all intermediate nodes (i.e., the outputs of all gates) in the order from primary inputs to those primary outputs that are in accordance with the reverse topological traversal order. We demonstrated the efficiency and effectiveness of the proposed method via a set of experimental verifications. In particular, we confirmed that the proposed method can verify practical GF multipliers (including those used in standardized elliptic curve cryptography) approximately 30 times faster on average and at most 170 times faster than the best conventional method.

show abstract

Section: Proposed Methodsmentioning

confidence: 99%

Section: Formal Verification Of Circuit Netlists Over Gf Arithmeticmentioning

confidence: 99%

Section: Formal Verification Of Circuit Netlists Over Gf Arithmeticmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations