Body-diode related losses in Shield-Plate FETs for SiP 12V-input DC/DC buck converters operating at high-frequency (4MHz)

Overcoming switching limits in silicon power MOSFETs with silicon‐based solutions

“…The assembly of all the previous elements in co-packaged or co-integrated solutions helps to reduce parasitic inductances in power and driving loops [3]. In the following subsections, a standard DrMOS is the selected approach to compactly package LS-FET, HS-FET, and driver [4].…”

SPICE analysis of RL and RC snubber circuits for synchronous buck DC-DC converters

“…The PWM, FET drivers, high-side FET and low-side FET are copackaged in a DrMOS module. More details on the chip can be found in [10]. The FETs are 30-V trench power FETs with a shielded gate [11].…”

“…The SPICE model consists of the PWM, FET drivers, highside and low-side FETs (which include the model of a body diode [10]), package parasitics, output inductor and the equivalent model of the input decoupling network (which consists of the metal plates on the PCB and the decoupling capacitors). The parameters of the SPICE models of active components are extracted from the process simulations, while the parasitic elements of the system are estimated by experiments and finite element simulations.…”

An Experimental Investigation of MOSFET Intrisic Body Diode Performance

“…A review of the literature in this field yielded little of use. Existing discussion in literature focuses instead on the experimental exploration of a specific device (or very narrow range of devices) [1][2][3][4], or perhaps discussing a die-level model to predict some parameters [5,6]. This is of little help in the derivation of a practical prediction from readily available information over a broad range of devices.…”