BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems

Abstract

In the past few years, Convolutional Neural Networks (CNNs) have seen a massive improvement, outperforming other visual recognition algorithms. Since they are playing an increasingly important role in fields such as face recognition, augmented reality or autonomous driving, there is the growing need for a fast and efficient system to perform the redundant and heavy computations of CNNs. This trend led researchers towards heterogeneous systems provided with hardware accelerators, such as GPUs and FPGAs. The vast majority of CNNs is implemented with floating-point parameters and operations, but from research, it has emerged that high classification accuracy can be obtained also by reducing the floating-point activations and weights to binary values. This context is well suitable for FPGAs, that are known to stand out in terms of performance when dealing with binary operations, as demonstrated in FINN, the state-of-theart framework for building Binarized Neural Network (BNN) accelerators on FPGAs. In this paper, we propose a framework that extends FINN to a distributed scenario, enabling BNNs implementation on embedded multi-FPGA systems.

Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs Distributed Systems

“…In our study presented in BNNsplit [5], we have obtained interesting reductions in terms of occupied area and latency, as well as dissipated dynamic power. The promising results are due to the high level of parallelism and the reduced latency of FPGAs, which made them the best solution to this problem.…”

“…The neural network we chose is the same used in [5] (shown in Fig. 1), and it was divided as mentioned in previous sections.…”

“…The chosen split point is located at layer 5 -the increase of resource utilization generated by the fully connected layers (6 to 8) was not relevant and hence not reported in the figure. The significant growth of the area occupied on the board by the application is balanced out by the massive reduction in size of the data transferred between the layers, that begins with more than 12000 Bytes/img in output at layer 0 and reaches a value of only 64 Bytes/img at layer 5 [5]. The percentage values of resource utilization are shown in detail in Table I.…”

“…In this work, we propose an analysis of the hardware resource usage while modifying the CNN splitting point and we describe how FARD [4], a framework to implement fog computing distributed system accelerators, is modified to deal with this kind of applications. This is a continuation of our previous work BNNsplit [5], where we explored splitting strategies for Xilinx FINN BNNs [6]. With respect to the previous work, where the division of the network was performed in order to minimize the amount of data that is sent from one layer to another, now it takes into consideration balancing the amount of hardware resources on each node.…”

Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

“…BNNs can directly replace the multiply-accumulate operations by simple XNOR and popcount operations. Therefore, their greatly reduced computational workload enables the use of DNNs on edge devices, and several accelerator designs for BNN have been proposed [22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38].…”