BMC via on-the-fly determinization

Jussila, Toni; Heljanko, Keijo; Niemelä, Ilkka

doi:10.1007/s10009-004-0178-1

Cited by 13 publications

(2 citation statements)

References 11 publications

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“…The set of benchmarks 2 used in the experiments consists of instances from various application domains, for which Boolean circuits offer a natural representation form: super-scalar processor verification [50], integer factorization based on hardware multipliers [43], equivalence checking of hardware multipliers [26], bounded model checking (BMC) for deadlocks in asynchronous parallel systems represented as labelled transition systems (LTS) [32], and linear temporal logic (LTL) BMC of finite state systems with a compact encoding [36]. We use standard PCs with 2-GHz AMD 3200+ processors and two gigabytes of memory running Linux, and apply a timeout of one hour and a memory limit of one gigabyte to each SAT solver execution.…”

Section: Methodsmentioning

confidence: 99%

Limitations of restricted branching in clause learning

Järvisalo¹,

Junttila²

2009

Constraints

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The techniques for making decisions, that is, branching, play a central role in complete methods for solving structured instances of constraint satisfaction problems (CSPs). In this work we consider branching heuristics in the context of propositional satisfiability (SAT), where CSPs are expressed as propositional formulas. In practice, there are cases when SAT solvers based on the Davis-PutnamLogemann-Loveland procedure (DPLL) benefit from limiting the set of variables the solver is allowed to branch on to so called input variables which provide a strong unit propagation backdoor set to any SAT instance. Theoretically, however, restricting branching to input variables implies a super-polynomial increase in the length of the optimal proofs for DPLL (without clause learning), and thus input-restricted DPLL cannot polynomially simulate DPLL. In this paper we settle the case of DPLL with clause learning. Surprisingly, even with unlimited restarts, input-restricted clause learning DPLL cannot simulate DPLL (even without clause learning). The opposite also holds, and hence DPLL and input-restricted clause learning DPLL are polynomially incomparable. Additionally, we analyze the effect of input-restricted branching on clause learning solvers in practice with various structured real-world benchmarks.

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Section: Methodsmentioning

confidence: 99%

Limitations of restricted branching in clause learning

Järvisalo¹,

Junttila²

2009

Constraints

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“…Related work includes [2], [3], where other non-standard encodings for concurrent systems are proposed. These are closely tied with system models, such as Petri nets and labeled transition systems, and thus are not readily extensible to systems with unbounded integer variables.…”

Section: Introductionmentioning

confidence: 99%

Bounded Model Checking of Concurrent Systems with Unbounded Integer Variables

Inoue

Tsuchiya

Kikuno

2011

2011 Second International Conference on Networking and Computing

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We discuss bounded model checking that uses a Satisfiability Modulo Theory (SMT) solver. The basic idea behind this model checking approach is to reduce the model checking problem to the satisfiability problem of a formula of some logic. Recent advances in SMT solvers make this particular approach significantly attractive. However, it does not work effectively in verification of concurrent systems, because the size of the formula blows up if the system has high concurrency. To overcome this, we adopt a different encoding for concurrent systems from the standard one. This encoding allows a compact formula representation of the behavior of concurrent systems. In this paper, we focus our attention on the verification of concurrent systems with unbounded integer variables and show how the new encoding helps improve the performance of model checking.

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Efficient encoding for bounded model checking of timed automata

Chen

et al. 2017

IEEJ Transactions Elec Engng

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Bounded model checking (BMC) of timed automata has been successfully applied to verify concurrent real‐time systems, but its scalability is still limited by the large bound required to find counter‐example, the efficiency of the decision procedure which is employed to solve the BMC formula, as well as the large search space for solving satisfiability of the resulting formula. In this paper, we present a systemic encoding scheme to attack all the above three problems. To attack the first problem, we first encode a discrete action followed by a time delay as a composed transition to cut the BMC steps which are used to characterize the time elapse. Then we take advantage of the local time semantics to allow more independent actions to be executed in parallel, which further reduces the required number of BMC steps and hence also the formula size. To employ a more efficient decision procedure, we also translate the linear arithmetic encoding of timed automata to a difference logic formula which can be solved more efficient by a satisfiability modulo theory solver. To address the last problem, we employ explicit‐state partial order reduction idea of only executing some of the enabled transitions to add additional constrains to eliminate some redundant multi‐step executions, thus restricting the search space. Experimental results show that our encoding performs significantly better than previous encodings. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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BMC via on-the-fly determinization

Cited by 13 publications

References 11 publications

Limitations of restricted branching in clause learning

Limitations of restricted branching in clause learning

Bounded Model Checking of Concurrent Systems with Unbounded Integer Variables

Efficient encoding for bounded model checking of timed automata

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