BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management

Gruian, Flavius; Westmijze, Mark

doi:10.1109/synasc.2007.12

Cited by 9 publications

(9 citation statements)

References 10 publications

(12 reference statements)

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“…the designer should profile the application(s) in order to detect hot regions. This can be carried out either on a desktop Java environment (less accurate) using, for instance VisualVM [23], or using specific simulators for JOP (which offers either high-level JVM simulation or VHDL simulation [26]) or BlueJEP (which can provide high level simulation via BSV tools [11]). Next (step 2.…”

Section: Design Flow Overviewmentioning

confidence: 99%

“…Since our hardware JVM is intended for accelerator generation or processor extensions for JOP/BlueJEP, we use the memory view and executable image characteristic to these processors (for details see [11,24]). The current implementation uses an opb bus interface with the external memory, in order to fit together with our versions of JOP and Blue-JEP.…”

Section: Object Accessmentioning

confidence: 99%

“…Bluespec has received attention both from industry and academia, and a number of rather complex designs written using BSV have been published (e.g. [5,6,11,13,14,33]). …”

mentioning

confidence: 99%

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Java bytecode to hardware made easy with bluespec system verilog

Gruian

Arslan

2012

Proceedings of the 10th International Workshop on Java Technologies for Real-Time and Embedded Systems

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This paper presents a method for translation of Java bytecode sequences into synthesizable hardware, using the Bluespec SystemVerilog (BSV) environment. At the core of our approach lies a BSV description of a subset of Java bytecodes, that can be used to directly translate bytecode sequences into a BSV specification. The result is intended as an accelerator for existing Java processors (JOP, BlueJEP) or even standalone hardware. Preliminary evaluation shows our solution to produce hardware on par with established methods (area/performance), while supporting rare features (e.g. easy to automate, method calls and recursion).

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Section: Design Flow Overviewmentioning

confidence: 99%

Section: Object Accessmentioning

confidence: 99%

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Java bytecode to hardware made easy with bluespec system verilog

Gruian

Arslan

2012

Proceedings of the 10th International Workshop on Java Technologies for Real-Time and Embedded Systems

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“…Quite unconventional is the bypass option where the execution stage can be skipped by individual instructions. BlueJEP can be configured to use a memory management unit that performs mark-compact based garbage collection in hardware [14].…”

Section: Bluejepmentioning

confidence: 99%

Hardware Support for Embedded Java

Schoeberl

2011

Distributed, Embedded and Real-Time Java Systems

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“…All the IPs except the processor and the MMU are in fact standard cores from the Xilinx EDK library. For more flexibility, the architecture can be configure with MMU, or without MMU, in which case the garbage collection and memory management is carried out in software [8]. A debug configuration facilitates interfacing the system with Chipscope cores [17], for monitoring processor and bus signals.…”

Section: The Designmentioning

confidence: 99%

VHDL vs. Bluespec system verilog

Gruian

Westmijze

2008

Proceedings of the 2008 ACM Symposium on Applied Computing

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This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BlueJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.

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BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management

Cited by 9 publications

References 10 publications

Java bytecode to hardware made easy with bluespec system verilog

Java bytecode to hardware made easy with bluespec system verilog

Hardware Support for Embedded Java

VHDL vs. Bluespec system verilog

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