BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation

Abstract

Current computer architecture research relies heavily on architectural simulation to obtain insight into the cycle-level behavior of modern microarchitectures. Unfortunately, such architectural simulations are extremely time-consuming. Sampling is an often-used technique to reduce the total simulation time. This is achieved by selecting a limited number of samples from a complete benchmark execution. One important issue with sampling, however, is the unknown hardware state at the beginning of each sample. Several approaches have been proposed to address this problem by warming up the hardware state before each sample. This paper presents the boundary line reuse latency (BLRL) which is an accurate and efficient warmup strategy. BLRL considers reuse latencies (between memory references to the same memory location) that cross the boundary line between the pre-sample and the sample to compute the warmup that is required for each sample. This guarantees a nearly perfect warmup state at the beginning of a sample. Our experimental results obtained using detailed processor simulation of SPEC CPU2000 benchmarks show that BLRL significantly outperforms the previously proposed memory reference reuse latency (MRRL) warmup strategy. BLRL achieves a warmup that is only half the warmup for MRRL on average for the same level of accuracy.

ESESC: A fast multicore simulator using Time-Based Sampling

“…Accelerating sampling: Different techniques are proposed to accelerate a sampling-based simulation such as native or hardware-accelerated methods(e.g., [9]), checkpoint based methods (e.g., [27]), or limited warmup (e.g., [11]). We implemented BLRL [11] but it did not reduce the simulation time in our setup (memory warmup is very fast in our setup, and smaller intervals reduce the speed of functional emulation, thereby diminishing the benefit).…”

“…We implemented BLRL [11] but it did not reduce the simulation time in our setup (memory warmup is very fast in our setup, and smaller intervals reduce the speed of functional emulation, thereby diminishing the benefit). Ekman et al [12] use a matched-pair technique to reduce the number of samples comparing different architectures running multiprogram applications.…”

TaskPoint: Sampled simulation of task-based programs

“…Warming in Multi-Threaded Simulations: Warming for single-threaded simulations has been extensively studied [1,2,12,13,14,30]. The technique used by the BarrierPoint methodology combines two existing methodologies, namely functional warming [13] and checkpointing [14].…”

Finding Stress Patterns in Microprocessor Workloads

“…For example, the architecture starting image (registers and memory state) can be set through fastforwarding or through checkpointing [26,28]; and the microarchitecture starting image (caches, branch predictors, etc.) can be estimated with microarchitecture state warmup techniques -there is a wealth of literature covering this area, see for example [5,8,12,19,26,28,29].…”