Block placement with symmetry constraints based on the O-tree non-slicing representation

Pang, Yingxin; Balasa, Florin; Lampaert, Koen; Cheng, Chung‐Kuan

doi:10.1145/337292.337545

Cited by 70 publications

(62 citation statements)

References 8 publications

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“…A B*-tree based method is proposed in [7] for handling both 1-D and 2-D symmetry constraints. Another symmetry-constrained analog placement work [8] uses O-tree representation. In [9], a symmetry-aware placement work is proposed based on Transitive Closure Graphs (TCG) data structure.…”

Section: Previous Work With Symmetry Constraintsmentioning

confidence: 99%

Regularity-constrained floorplanning for multi-core processors

Chen

2011

Proceedings of the 2011 International Symposium on Physical Design

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Multi-core technology becomes a new engine that drives performance growth for both microprocessors and embedded computing. This trend asks chip floorplanners to consider regularity constraint since identical processing/memory cores are preferred to form an array in layout. As chip core count keeps growing, manual floorplanning will be inefficient on the solution space exploration while conventional floorplanning algorithms do not address the regularity constraint. In this work, we investigate how to enforce regularity constraint in a simulated-annealing based floorplanner. We propose a simple and effective technique for encoding the regularity constraint in sequence-pairs. To the best of our knowledge, this is the first work on regularityconstrained floorplanning in the context of multi-core processor designs. Experimental comparison with a semi-automatic method shows that our approach yields an average of 22% less wirelength and mostly smaller area.

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Section: Previous Work With Symmetry Constraintsmentioning

confidence: 99%

Regularity-constrained floorplanning for multi-core processors

Chen

2011

Proceedings of the 2011 International Symposium on Physical Design

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“…Balasa et al derived the symmetric-feasible conditions for several popular floorplan representations including sequence pairs (SPs) [8], O-tree [9], and binary trees [10]. To explore the solution space in the symmetric-feasible binary trees, they augmented the B * -tree [11] using various data structures, including segment trees [3], [12], red-black trees [13], and deterministic skip lists [14].…”

Section: A Previous Workmentioning

confidence: 99%

Analog Placement Based on Symmetry-Island Formulation

Lin

Chang

Lin³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B * -tree representation, we propose automatically symmetric-feasible (ASF) B * -trees to directly model the placement of a symmetry island. We then present hierarchical B * -trees (HB * -trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B * -tree or an HB * -tree is the same as that for a plain B * -tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.

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“…The solution space is much smaller in comparison with that of absolute representation, but complicated computations are needed for checking symmetry feasibility and adjusting the module positions to satisfy the constraints. Topological representations like sequencepairs [11], O-tree [4], B*-trees [3] have been applied to handle symmetry constraints in [1,12,2]. Comparisons in [2] have shown that the segment tree approach [2] has out-performed others in both solution quality and run time.…”

Section: Introductionmentioning

confidence: 99%

Analog placement with symmetry and other placement constraints

Tam

Young

Chu

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously. The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously. Instead of handling the constraints by having a penalty term in the cost function to penalize violations, a unified method is proposed that, by adjusting the edge weights in a pair of constraint graphs, can try to satisfy all the placement and symmetry constraints simultaneously in a candidate floorplan solution. The maximum distance of the modules in a symmetry group from the corresponding symmetry axis will be minimized in this weight adjusting step, in order to minimize the total packing area. We have compared our method with the most updated results on this problem [2] when there are only symmetry constraints and results show that our approach can give solutions of better quality, in an acceptable amount of run time. We will also demonstrate the effectiveness of our approach in handling different types of constraints simultaneously by testing on data sets with both symmetry and other placement constraints, and the results are very promising.

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Block placement with symmetry constraints based on the O-tree non-slicing representation

Cited by 70 publications

References 8 publications

Regularity-constrained floorplanning for multi-core processors

Regularity-constrained floorplanning for multi-core processors

Analog Placement Based on Symmetry-Island Formulation

Analog placement with symmetry and other placement constraints

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