Block-interleaving based parallel CRC computation for multi-processor systems

Cho, Junho; Sung, B.N.; Sung, Wonyong

doi:10.1109/sips.2010.5624807

Cited by 7 publications

(6 citation statements)

References 8 publications

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“…The algorithms as mentioned above are all fine-grained parallel methods. In recent years, coarse-grained parallel CRC algorithms based on multi-processor architectures are proposed [9], [11]. These algorithms can be easily combined with fine-grained CRC algorithms to improve performance further.…”

Section: Related Workmentioning

confidence: 99%

“…Notice that, this algorithm induces folk-join overhead for every n × N bytes. In order to minimize the synchronization overhead, Cho et al [9] proposed a block-interleaving based parallel CRC algorithm. This algorithm is similar to [11], except that a propagation step, instead of the combination step mentioned in [11], is performed so that the dependency problem is resolved.…”

Section: Related Workmentioning

confidence: 99%

“…In order to improve the performance of the CRC generation process, a number of software-based algorithms have been proposed in the past. Among these algorithms, the most commonly used today are table lookup based CRC [3], [4], parallel table lookup based CRC [5]- [7], symbolic simplification based CRC [8] and multi-processor based parallel CRC [9]- [11].…”

Section: Introductionmentioning

confidence: 99%

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Exploring Various Levels of Parallelism in High-Performance CRC Algorithms

Chi

2019

IEEE Access

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Modern processors have increased the capabilities of instruction-level parallelism (ILP) and thread-level parallelism (TLP). These resources, however, typically exhibit poor utilization on conventional cyclic redundancy check (CRC) algorithms. In this paper, various levels of parallelism in high-performance CRC algorithms are investigated. The main idea of the proposed algorithms is to make full utilization of modern processors, from the perspective of both instruction-level and thread-level parallelism. First, a finegrained algorithm executes the CRC computation in an interleaved manner, so that multiple independent data flows can be processed simultaneously. This algorithm allows instruction-level parallelism, which triples and doubles the performance of the existing slicing-by-4 and slicing-by-8 algorithms, respectively. Second, a coarse-grained algorithm can ideally deal with data in a parallel way by parallelizing a family of serial CRC generating algorithms. Therefore, this algorithm allows thread-level parallelism, which can make full use of multi-core computing capability. As a result, it achieves a speedup that is almost equal to the number of threads used. In addition, both fine-grained and coarse-grained algorithms can be applied together to achieve high throughput further. (This is an extended version of a paper that appeared at the 28th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC) in Montreal, QC, Canada, in 2017.) INDEX TERMS Cyclic redundancy check (CRC), fault detection, parallel algorithms.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Exploring Various Levels of Parallelism in High-Performance CRC Algorithms

Chi

2019

IEEE Access

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“…Cyclic redundancy codes (CRCs) form a powerful class of codes suited especially for the detection of burst errors in data storage and communication applications [6]. In the traditional hardware implementations, a simple shift-registerbased circuit performs the computation by handling the data one bit at a time [1].…”

Section: Introductionmentioning

confidence: 99%

“…Although some algorithms have been proposed for parallel CRC calculation they increase the length of the worst case timing path as well as the required area and power consumption [6], [8], [9], [11]. Therefore, we seek an alternative way to implement CRC hardware to speed up the CRC calculation with reasonable area.…”

Section: Introductionmentioning

confidence: 99%

An approach to exploiting proper multiples of the generator polynomial in parallel CRC computation

Mehrabian

Mozafari

Zolfaghari

2012

2012 IEEE International Conference on Computer Science and Automation Engineering (CSAE)

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Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. In this method, the transmitter divides of the message by an agreed upon polynomial called the generator and concatenates the calculated residue to the message. The receiver divides what it receives by the generator again. A zero residue indicates error-free transmission and a nonzero residue is interpreted as an error. These calculations are traditionally performed using serial circuits called LFSR especially in serial communications such as the case of the Ethernet protocol. But in parallel communications such as USB, and also integrity checking applications, this method is not efficient enough. In this paper, a new parallel algorithm for parallel CRC calculation is proposed and evaluated. The proposed algorithm exploits mathematical properties of a special family of generator polynomials named OZZ (One-Zero-Zero) polynomials. In this approach, we feedbacks are eliminated and pipelined calculations are used to obtain 32-bit CRC in the SMIC 0.35 m CMOS technology. ___________________________________ 978-1-4673-0089-6/12/$26.00 ©2012 IEEE

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A Parallel CRC Algorithm Based on Symbolic Polynomial

Zhang

2012

Advances in Intelligent and Soft Computing

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Block-interleaving based parallel CRC computation for multi-processor systems

Cited by 7 publications

References 8 publications

Exploring Various Levels of Parallelism in High-Performance CRC Algorithms

Exploring Various Levels of Parallelism in High-Performance CRC Algorithms

An approach to exploiting proper multiples of the generator polynomial in parallel CRC computation

A Parallel CRC Algorithm Based on Symbolic Polynomial

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