Blasting through the Front-End Bottleneck with Shotgun

Kumar, Rakesh; Grot, Boris; Nagarajan, Vijay

doi:10.1145/3173162.3173178

Cited by 38 publications

(62 citation statements)

References 16 publications

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“…For each trace, we first warmup for 50M instructions and then report performance for the next 50M instructions. BTB designs: Based on the performance improvement and storage overhead, we use the following recent works for our evaluation: (i) Shotgun [3] (ii) SN4L+Dis+BTB [4], (iii) Skewed BTB [12] and (iv) FDIP-X [11]. Table II provides the details about these techniques.…”

Section: Evaluation a Evaluation Methodologymentioning

confidence: 99%

“…Prefetch or demand blocks which are filled into the L1I cache are predecoded, and the branches are stored in the Air BTB. Shotgun BTB [3]: Shotgun BTB proposes a new BTB design segregated by the type of control flow jumps. It uses three kinds of BTB: (i) C-BTB for conditional branches, (ii) U-BTB for unconditional branches, and (iii) RIB for return.…”

Section: Related Workmentioning

confidence: 99%

“…State-of-the-art techniques for reducing front-end bottlenecks like Shotgun [3] and SN4L+Dis+BTB [4] employ L1I prefetcher to prefetch cache blocks in the L1I. These techniques decode the prefetched cache blocks and pre-fill the branches into the BTB.…”

Section: Introductionmentioning

confidence: 99%

“…The PN-cache adds extra latency to the critical path of accessing the BTB. Opportunity: Figure 1 shows average performance improvement with various state-of-the-art BTB designs [3], [4], [11], [12] normalized to a baseline system [13] with two-level BTB, a 128-entry L1 BTB and an 8192-entry L2 BTB. We do not show the performance and area overheads for Phantom BTB [14], [15] and Confluence [16] for 8K-entry BTB as it demands significant storage.…”

Section: Introductionmentioning

confidence: 99%

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Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Gupta¹,

Panda²

2021

Preprint

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High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequent. Recent industry trend shows usage of large BTBs (100s of KB per core) that provide performance closer to the ideal BTB along with a decoupled front-end that provides efficient fetch-directed L1I instruction prefetching. On the other hand, techniques proposed by academia, like BTB prefetching and using retire order stream for learning, fail to provide significant performance with modern-day processor cores that are deeper and wider.We solve the problem fundamentally by increasing the storage density of the last-level BTB. We observe that not all branch instructions require a full branch target address. Instead, we can store the branch target as a branch offset, relative to the branch instruction. Using branch offset enables the BTB to store multiple branches per entry. We reduce the BTB storage in half, but we observe that it increases skewness in the BTB. We propose a skewed indexed and compressed last-level BTB design called MicroBTB (MBTB) that stores multiple branches per BTB entry. We evaluate MBTB on 100 industry-provided server workloads. A 4K-entry MBTB provides 17.61% performance improvement compared to an 8K-entry baseline BTB design with a storage savings of 47.5KB per core.

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Section: Evaluation a Evaluation Methodologymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Gupta¹,

Panda²

2021

Preprint

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“…To mitigate the high latency cost of page walks, Translation Lookaside Buffers (TLBs) cache the most recently used virtualto-physical translations. Despite the use of multi-level TLB hierarchies and other hardware and software schemes for accelerating address translation, frequent data TLB misses still cause significant performance degradation due to long miss penalties [30,32,40,47,54,58,63]. In response, the research community has proposed many techniques for reducing the overhead of address translation associated with data accesses [36,38,53,56,60,66,68,69,73,74,79,82].…”

Section: Introductionmentioning

confidence: 99%

Morrigan: A Composite Instruction TLB Prefetcher

Vavouliotis¹,

Alvarez

Grot

et al. 2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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The effort to reduce address translation overheads has typically targeted data accesses since they constitute the overwhelming portion of the second-level TLB (STLB) misses in desktop and HPC applications. The address translation cost of instruction accesses has been relatively neglected due to historically small instruction footprints. However, state-of-the-art datacenter and server applications feature massive instruction footprints owing to deep software stacks, resulting in high STLB miss rates for instruction accesses.This paper demonstrates that instruction address translation is a performance bottleneck in server workloads. In response, we propose Morrigan, a microarchitectural instruction STLB prefetcher whose design is based on new insights regarding instruction STLB misses. At the core of Morrigan there is an ensemble of table-based Markov prefetchers that build and store variable length Markov chains out of the instruction STLB miss stream. Morrigan further employs a sequential prefetcher and a scheme that exploits page table locality to maximize miss coverage. An important contribution of the work is showing that access frequency is more important than access recency when choosing replacement candidates. Based on this insight, Morrigan introduces a new replacement policy that identifies victims in the Markov prefetchers using a frequency stack while adapting to phase-change behavior. On a set of 45 industrial server workloads, Morrigan eliminates 69% of the memory references in demand page walks triggered by instruction STLB misses and improves geometric mean performance by 7.6%. CCS CONCEPTS• Software and its engineering → Virtual memory; • Applied computing → Data centers.

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