BLAS Comparison on FPGA, CPU and GPU

Kestur, Srinidhi; Davis, John D.; Williams, Oliver J.

doi:10.1109/isvlsi.2010.84

Cited by 125 publications

(51 citation statements)

References 9 publications

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“…We use some routines from the Basic Linear Algebra Subprograms (BLAS) [36]- [38] and the Linear Algebra PACKage (LAPACK) [39], [40] for key parts of the likelihood computations. Thereby we can guarantee high and portable performance of the computational core routines across a large variety of present and future platforms (E.g., [41]). …”

Section: Methodsmentioning

confidence: 99%

SlimCodeML: An Optimized Version of CodeML for the Branch-Site Model

Schabauer

Valle

Pacher

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Abstract-CodeML (part of the PAML package) implements a maximum likelihood-based approach to detect positive selection on a specific branch of a given phylogenetic tree. While CodeML is widely used, it is very compute-intensive. We present SlimCodeML, an optimized version of CodeML for the branch-site model. Our performance analysis shows that SlimCodeML substantially outperforms CodeML (up to 9.38 times faster), especially for large-scale genomic analyses.

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Section: Methodsmentioning

confidence: 99%

SlimCodeML: An Optimized Version of CodeML for the Branch-Site Model

Schabauer

Valle

Pacher

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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“…Moreover, many comparative studies indicate that Field Programmable Gate Arrays (FPGAs) can often achieve better comprehensive properties than other platforms in most cases. For example, in the work of Zou et al [9], the efficiency of the FPGA implementation of the Smith-Waterman Algorithm is 3.4× compared to the Graphics Processing Unit (GPU) and over 40× compared to the Central Processing Unit (CPU), while Kestur et al [10] demonstrated that FPGA has similar performance at higher energy efficiency compared to the CPU and GPU platforms.…”

Section: Introductionmentioning

confidence: 99%

Embedded Implementation of VHR Satellite Image Segmentation

2017

Architecture‐Aware Optimization Strategies in Real‐time Image Processing

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Processing and analysis of Very High Resolution (VHR) satellite images provide a mass of crucial information, which can be used for urban planning, security issues or environmental monitoring. However, they are computationally expensive and, thus, time consuming, while some of the applications, such as natural disaster monitoring and prevention, require high efficiency performance. Fortunately, parallel computing techniques and embedded systems have made great progress in recent years, and a series of massively parallel image processing devices, such as digital signal processors or Field Programmable Gate Arrays (FPGAs), have been made available to engineers at a very convenient price and demonstrate significant advantages in terms of running-cost, embeddability, power consumption flexibility, etc. In this work, we designed a texture region segmentation method for very high resolution satellite images by using the level set algorithm and the multi-kernel theory in a high-abstraction C environment and realize its register-transfer level implementation with the help of a new proposed high-level synthesis-based design flow. The evaluation experiments demonstrate that the proposed design can produce high quality image segmentation with a significant running-cost advantage.

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“…Custom built FPGA hardware is more efficient than general purpose components [10], [7]. Power-consumption -a first-class constraint This work has been funded by the Artemis PaPP project number 295440 -can also be reduced compared to CPUs or GPUs [11], [8]. FPGAs can be configured to have far more parallel throughput than their general purpose counterparts.…”

Section: Introductionmentioning

confidence: 99%

Empowering OpenMP with automatically generated hardware

Podobas

Brorsson

2016

2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

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Abstract-OpenMP enables productive software development that targets shared-memory general purpose systems. However, OpenMP compilers today have little support for future heterogeneous systems -systems that will more than likely contain Field Programmable Gate Arrays (FPGAs) to compensate for the lack of parallelism available in general purpose systems.We have designed a high-level synthesis flow that automatically generates parallel hardware from unmodified OpenMP programs. The generated hardware is composed of accelerators tailored to act as hardware instances of the OpenMP task primitive. We drive decision making of complex details within accelerators through a constraint-programming model, minimizing the expected input from the (often) hardware-oblivious software developer.We evaluate our system and compare them to two state of the art architectures -the Xeon PHI and the AMD Opteron -where we find our accelerators to perform on par with the two ASIC processors.

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BLAS Comparison on FPGA, CPU and GPU

Cited by 125 publications

References 9 publications

SlimCodeML: An Optimized Version of CodeML for the Branch-Site Model

SlimCodeML: An Optimized Version of CodeML for the Branch-Site Model

Embedded Implementation of VHR Satellite Image Segmentation

Empowering OpenMP with automatically generated hardware

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