Blade -- A Timing Violation Resilient Asynchronous Template

Abstract

Resilient designs offer the promise to remove increasingly large margins due to process, voltage, and temperature variations and take advantage of average-case data. However, proposed synchronous resilient schemes have either suffered from metastability or require modifying the architecture to add replaybased logic that recovers from timing errors, which leads to high timing error penalties and poses a design challenge in modern processors. This paper presents an asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. The template is supported by an automated design flow that synthesizes synchronous RTL designs to gate-level asynchronous Blade designs. The benefits of this flow are illustrated on Plasma, a 3-stage OpenCore MIPS CPU. Our results demonstrate that a nominal area overhead of the asynchronous template of less than 10% leads to a 19% performance boost over the synchronous design due to average-case data and a 30-40% improvement when synchronous PVT margins are considered. EDL

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

“…Consequently, any SET that causes a latch to go into metastability will be detected and mitigated by re-opening and closing the latch, essentially re-sampling the data. This is in contrast to its timing-resilient inspiration [18] which, relying on worst-case timing analysis, does not re-sample the data but instead mitigates timing violations only by slowing down downstream pipeline stages.…”

“…This paper explores the possibility of building an efficient SET-resilient technique that uses standard cell libraries and pays a performance penalty only when an SET occurs. The proposed approach is inspired by an asynchronous bundleddata template that is timing-resilient [18], exhibiting high performance when no timing errors occur and gracefully slowing down in the presence of timing errors. However, unlike timing-resilient designs that can assume that the timing of signals is governed by a notion of worst-case delay, SETresilient circuits must account for the fact that SETs can occur at any time.…”

Reactive clocks with variability-tracking jitter

“…The main drawback of Razor-like techniques is the significant area overhead for error detection and correction, which involves intricate schemes to cope with metastability and architectural support for flushing the pipeline and replaying instructions. Blade [20] reduces the overheads of Razor by incorporating reconfigurable delay lines, error detecting latches and asynchronous structures, albeit it still requires modifications in the circuitry. Along the same lines, Tribeca [21] proposes to use ECC-protected data and local recovery mechanisms to reduce margins and work at nominal conditions.…”

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework

“…BD promises to reduce power and increase performance at area/power costs similar to those of synchronous circuits [5], [6]. BD templates are thus increasingly popular [6]- [8], and different schemes exist for their implementation, e.g. desynchronization [9], Mousetrap [10] and Blade [8].…”

“…BD templates are thus increasingly popular [6]- [8], and different schemes exist for their implementation, e.g. desynchronization [9], Mousetrap [10] and Blade [8].…”