Bit significance based reconfigurable approximate restoring dividers and square rooters

Arya, Neelam; Soni, Teena; Pattanaik, Manisha; Sharma, Govind

doi:10.1016/j.mejo.2020.104861

Cited by 4 publications

(1 citation statement)

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“…These hardware architectures are based on a 2's complement representation, described in VHDL, and synthesized into a 65 nm CMOS dedicated ASIC. This paper [30] proposes a reconfigurable approximate recovery of dividers and square roots based on bit weight to improve energy efficiency. Configurable subtractor cells (CSCs) are proposed, which work accurately and approximately, along with simplified and scalable overflow detection hardware as the main design unit.…”

Section: Previous Workmentioning

confidence: 99%

QIAD: A quadratic interpolation approximate divider

Liu

Wang

Liu

2023

IEICE Electron. Express

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The balance between computational performance and power consumption is a key constraint in computing systems, with integrated circuit technology posing a bottleneck. Approximate computation can trade off accuracy for performance or power improvement in error-tolerant scenarios. Division, with high computational demands and latency, is a bottleneck for computational efficiency. We propose a quadratic interpolation approximate divider (QIAD) based on multiplicative division, which has superior statistical performance. The design is simulated and synthesized at TSMC 65 nm process and tested on image color quantization, showing the best quantization effect using evaluation indicators such as PSNR, MSE, and SSIM.

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Section: Previous Workmentioning

confidence: 99%