Bit selection algorithm suitable for high-volume production of SRAM-PUF

Xiao, Kun; Rahman, Mostafizur; Forte, Domenic; Huang, Yu; Su, Mei; Tehranipoor, Mohammad

doi:10.1109/hst.2014.6855578

Cited by 112 publications

(66 citation statements)

References 13 publications

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“…The uniformity of the 153 sequences of 100 c kij correlation bits was analyzed using the NIST Frequency Test. The proportions of sequences with a p-value bigger than 0.01 (a confidence of 99%) verify the condition in Equation (12) and the distributions of p-values verify Equation (13). It can therefore be concluded, with a confidence of 99%, that the IDs provided by the same SRAM are not correlated.…”

Section: A Advantages For the Generation Of Identifiers 1) Independementioning

confidence: 72%

“…This is known as the bit flipping problem [6]- [12]. In identification applications, some bit flipping is allowable provided that the identifiers generated by genuine and fake memories are sufficiently different.…”

mentioning

confidence: 99%

“…Several authors have proposed experimentally characterizing the behavior of the start-up values at multiple environmental temperatures (at least three temperatures), by using a temperature chamber or a temperature forcing system to control the operating temperature of the memory [17], [18]. As an alternative to this exhaustive characterization of many operating conditions, [12] proposed verifying two corner conditions (high-temperature low-power-supply-voltage and low-temperature low-powersupply-voltage), together with a neighborhood analysis within a memory word to select the most suitable cells for generating identifiers or keys. However, those corner conditions are not common to all SRAMs and neighborhood influence also depends on the particular SRAM in question (for example, strong location-based correlations are reported in [19] but not in other works).…”

mentioning

confidence: 99%

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Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

Baturone

Prada-Delgado

Eiroa³

2015

IEEE Trans.Inform.Forensic Secur.

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Abstract-This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard Static Random Access Memories, SRAMs. The method is based on classifying memory cells after evaluating their startup values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different Application Specific Integrated Circuits, ASICs, fabricated with 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, worst-case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst-case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in 90-nm TSMC technology occupies an active area of 42,025 μm 2 .

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Section: A Advantages For the Generation Of Identifiers 1) Independementioning

confidence: 72%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

Baturone

Prada-Delgado

Eiroa³

2015

IEEE Trans.Inform.Forensic Secur.

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“…If the resultant value after 15 evaluations of the cell's response is greater than 8, then the final value is classified as 1, or else it can be classified as 0. The concept of TMV has been discussed extensively in previous works by Mathew et al and Xiao et al [10,23]. The mathematical model of the TMV is a binomial counting process and, hence, the reduction in error rate can be calculated analytically.…”

Section: Temporal Majority Votingmentioning

confidence: 99%

“…A simple way to reduce the error rate is using a Temporal Majority Voting scheme [10,23]. For example, a simple 4-bit counter based TMV counts from 0 to 15 and hence can be used as 15-way voting.…”

Section: Temporal Majority Votingmentioning

confidence: 99%

On Improving Reliability of SRAM-Based Physically Unclonable Functions

Vijayakumar

Patil

Kundu

2017

JLPEA

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Physically unclonable functions (PUFs) have been touted for their inherent resistance to invasive attacks and low cost in providing a hardware root of trust for various security applications. SRAM PUFs in particular are popular in industry for key/ID generation. Due to intrinsic process variations, SRAM cells, ideally, tend to have the same start-up behavior. SRAM PUFs exploit this start-up behavior. Unfortunately, not all SRAM cells exhibit reliable start-up behavior due to noise susceptibility. Hence, design enhancements are needed for improving reliability. Some of the proposed enhancements in literature include fuzzy extraction, error-correcting codes and voting mechanisms. All enhancements involve a trade-off between area/power/performance overhead and PUF reliability. This paper presents a design enhancement technique for reliability that improves upon previous solutions. We present simulation results to quantify improvement in SRAM PUF reliability and efficiency. The proposed technique is shown to generate a 128-bit key in ≤0.2 µs at an area estimate of 4538 µm 2 with error rate as low as 10 −6 for intrinsic error probability of 15%.

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Recent Advances of Volatile Memristors: Devices, Mechanisms, and Applications

Wang

Yang

Mao

et al. 2020

Advanced Intelligent Systems

136

113

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Due to the rapid development of artificial intelligence (AI) and internet of things (IoTs), neuromorphic computing and hardware security are becoming more and more important. The volatile memristors, which feature spontaneous decay of device conductance, own the distinct combination of high similarity to the biological neurons and synapses and unique physical mechanisms. They are excellent candidates for mimicking the synaptic functions and ideal randomness source of the entropy for hardware‐based security. Herein, the recent advances of volatile memristors in devices, mechanisms, and application aspects are summarized. First, a brief introduction is presented to describe the switching type, materials, and temporal response of volatile memristors. Second, the volatile switching mechanisms are discussed and grouped into ion effects, thermal effects, and electrical effects. Third, attention is focused on the applications of volatile memristors for access devices, neuromorphic computing (artificial neurons and synapses), and hardware security (true random number generators and physical unclonable functions). Finally, major challenges and future outlook of volatile memristors for neuromorphic computing and hardware security are discussed.

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Bit selection algorithm suitable for high-volume production of SRAM-PUF

Cited by 112 publications

References 13 publications

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

On Improving Reliability of SRAM-Based Physically Unclonable Functions

Recent Advances of Volatile Memristors: Devices, Mechanisms, and Applications

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