Bit-parallel arithmetic in a massively-parallel associative processor

Scherson, Isaac D.; Kramer, David A.; Alleyne, Brian D.

doi:10.1109/12.166599

Cited by 19 publications

(22 citation statements)

References 7 publications

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“…This results in a poor resource utilisation since most bits in the underlying associative memory remain unused (masked-off) at each computational cycle. In order to overcome this inefficiency, Scherson et al [20] partitioned each memory word into a number of bit-planes, forming a matrix of storage cells (Fig. 8).…”

Section: Mapping a 2d-mesh Geometry Into The Hypercubementioning

confidence: 99%

“…The authors of Ref. [20] claimed that the ALU can be designed as a dynamic CMOS circuit minimising its complexity and thereby providing the capability for massive parallelism via VLSI implementation.…”

Section: Mapping a 2d-mesh Geometry Into The Hypercubementioning

confidence: 99%

“…This value has not been chosen randomly. Scherson et al [20] claimed that using the current VLSI technology, it is feasible to implement an associative processor chip where each processing element consists of 1 K bits of memory split into 5 bit planes as well as the associated control and networking circuitry. This gives a register length of up to 204 bits.…”

Section: Massively Parallel Processor Algorithms 43mentioning

confidence: 99%

“…Due to the rapid evolution of VLSI technology and the large regularity of this type of architecture, the cost of manufacturing associative memories with parallel access not only to the memory words but also to the individual bits in each word, has been dramatically decreased [19]. Additionally, the addition of arithmetic/logic circuits in each memory word is feasible, transforming it into a processing element [20]. These circuits are able to execute logical operations, such as OR and AND, in parallel on the bits in each processing element, thereby allowing the implementation of a word-parallel, bit-parallel, massively-parallel computing system.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Efficient binary and grey level morphological operations on a massively parallel processor

Svolos¹,

Konstantopoulos²,

Kaklamanis³

2004

Parallel Algorithms and Applications

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One of the most important features in image analysis and understanding is shape. Mathematical morphology is the image processing branch that deals with shape analysis. The definition of all morphological transformations is based on two primitive operations, i.e. dilation and erosion. Since many applications require the solution of morphological problems in real time, researching time efficient algorithms for these two operations is crucial.In this paper, efficient algorithms for the binary as well as the grey level dilation and erosion are presented and evaluated for an advanced associative processor. It is shown through simulation results that the above architecture is near optimal in the binary case and is also as efficient as the array processor with a 2D-mesh interconnection in the grey level case. Finally, it is proven that the implementation of this image processing machine is economically feasible.

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Section: Mapping a 2d-mesh Geometry Into The Hypercubementioning

confidence: 99%

Section: Mapping a 2d-mesh Geometry Into The Hypercubementioning

confidence: 99%

Section: Massively Parallel Processor Algorithms 43mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient binary and grey level morphological operations on a massively parallel processor

Svolos¹,

Konstantopoulos²,

Kaklamanis³

2004

Parallel Algorithms and Applications

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“…Compared to the associative processor of Figure 2, our model depicted in Figure 3 owns smaller PEs which are dedicated to a limited set of special operations, depending on their location along the data flow. They perform bit-parallel arithmetic [9] mostly shifts and additions plus some logarithms as described in [6]. With respect to the implemented algorithm, they are commanded by the control unit which plays the role of a global scheduler at the same time.…”

Section: Dedicated Hardware Architecturementioning

confidence: 99%

A scalable highly parallel VLSI architecture dedicated to associative computing algorithms

Layer¹,

Pfleiderer²

Research in Microelectronics and Electronics, 2005 PhD

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Low power, high speed and high flexibility are today's requirements for SoC (System On Chip) designers. Because average bandwidth at the side of main memory is crucial for system performance, our research focuses on the development of digital architectures for low-level and very highthroughput data processing. Based on an associative computing paradigm, this paper presents the implementation of a scalable associative processor dedicated to textual retrieval in huge databases by means of approximate matching techniques. It exposes the internal architecture of the system and shows an efficient use of pipelining within the scalable and highly parallel processing core. As a key feature to the architecture, the hardware implementation of sorting and merging algorithms based on comparator networks yields very short time for the ranking operations. Moreover, it permits to keep the final processing speed higher enough to reach the maximum peripheral data throughput.

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