Bit-level systolic arrays for IIR filtering

Knowles, S.C.; Woods, Roger; McWhirter, J.G.; McCanny, J.V.

doi:10.1109/arrays.1988.18102

Cited by 18 publications

(5 citation statements)

References 8 publications

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“…Some current work has reported that the use of redundant arithmetic can be useful for the implementation of bit-level recursive systolic arrays [9], since the arithmetic evaluates from the most significant bit down, rather than the least significant bit up for binary arithmetic. Some work has also been reported on the use of residue arithmetic in bit-level systolic arrays [10], [11].…”

Section: Introductionmentioning

confidence: 99%

An efficient bit-level systolic cell design for finite ring digital signal processing applications

Jullien

Bird

Carr

et al. 1989

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. This paper presents design details for a bit-level systolic cell that has been recently introduced for implementing digital signal processing (DSP) operations over finite rings. This paper concentrates on the efficient construction of the basic cell, using a 3/z p-well CMOS technology. The design uses a 5-bit, 32-word dynamic ROM as the main computational element, and details of all elements of the cell are discussed with regard to minimizing the (Area.Period) product. The final cell design and simulation details are compared with a pipelined gated full-adder, designed in the same technology, which represents the most common type of binary bit-level systolic cell.It is shown that the (Area.Period) product of the binary cell is 68% greater than that of the finite ring cell, but the power of the finite ring cell, in implementing fixed coefficient inner product multiplications, is much greater than that of the binary cell. There are also advantages associated with the reduction of the connectivity across the dynamic range, including clock-skew reduction, ease of testing, and fault detection. The conclusion is that in certain classes of DSP operations, this new cell can offer more than an order of magnitude improvement in (Area.Period) product of complete bit-level systolic arrays, over its binary counterpart.

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Section: Introductionmentioning

confidence: 99%

An efficient bit-level systolic cell design for finite ring digital signal processing applications

Jullien

Bird

Carr

et al. 1989

J VLSI Sign Process Syst Sign Image Video Technol

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“…The on-line delay, in this case, is given by (4) where Cmar = max(lc1) 11. For a second-order direct…”

Section: Ma Algorithmmentioning

confidence: 99%

“…MSD-first systolic arrays accept the FIR input in bit-parallel form and roduce the output in skew-parallel form [4], [5], [67. The derivation and implementation of a radix-4 on-line MA algorithm is described in [l].…”

Section: Introductionmentioning

confidence: 99%

On-line arithmetic modules for recursive digital filters

Fernando¹,

Ercegovac²

[1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems &Amp; Computers

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A new on-line multiply-add M A ) module is designed for implementing Seconb-Order Direct-Form IIR filters. The M A module is implemented an a 0.7-micron HCMOS gate array technology. A n array of M A modules is developed t o perform the secondorder recursive computations at 128Msamples/second with two levels of scattered lookahead. A new conventional (bit-parallel) design using similar lookahead is implemented in the same technology. The 104Msam-ple/second conventional design implements a carryfree recursive loop and uses radix-4 recoding to reduce the number of partial products. The on-line array has a sampling rate higher than the conventional implementation for 1% or more bits.

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“…In [3] a pipelined MSB first twoport adaptor is described, based on the arithmetic principles described in [7]. It uses a redundant number system with a digit set [ -1,0,1) .…”

Section: Pipelined Msb First Two Port Adaptorsmentioning

confidence: 99%

Low latency architectures for wave digital filters

Harris-Dowsett¹,

Surnmerfield²

1993 IEEE International Symposium on Circuits and Systems

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Wave digital filters constructed of networks of two port adaptors have a number of desirable characteristics that make then attractive candMates for VLSI implementation. Since these systems are recurslve, pipelining, and hence high data throughput, requires a low latency, high throughput, hardware structure for the two port adaptor. This design problem has been addressed recently in two main approaches. Firstly with systolic array techniques based on fsb first pipelining that exploit the low coefficient wordkngth properties of wave digital filters and secondly with msb first pipelining based on signed digit number systems. This paper extends, compares and contrasts these methods, presentsa new hardware scheme and details which arrangements are best suited for particular filtering applications.

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Bit-level systolic arrays for IIR filtering

Cited by 18 publications

References 8 publications

An efficient bit-level systolic cell design for finite ring digital signal processing applications

An efficient bit-level systolic cell design for finite ring digital signal processing applications

On-line arithmetic modules for recursive digital filters

Low latency architectures for wave digital filters

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