Bit-Level Analysis of an SRT Divider Circuit.

Bryant, Randal E.

doi:10.21236/ada294842

Cited by 7 publications

(2 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…From a verification point of view, one of the most difficult parts in such complicated designs is arithmetic datapaths and their components, such as multipliers and dividers. Most of hardware verification tools are based on bitlevel methods like Binary Decision Diagrams (BDDs) or Satisfiability (SAT) solvers that are not scalable because they suffer from space and time explosion problems when dealing with large arithmetic circuits [1] [2]. To alleviate this problem, word-level Decision Diagrams like Binary Moment Diagrams (BMDs), *BMDs and K*BMDs have been proposed [3].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A dynamic specification to automatically debug and correct various divider circuits

Haghbayan

Alizadeh

2016

Integration

View full text Add to dashboard Cite

This paper presents a formal technique to verify and debug division circuits on fixed point numbers. The proposed technique is based on a reverse-engineering mechanism of obtaining a high level model of the gate level implementation and also introducing an intermediate representation of the specification that makes equivalence checking between two models possible. The main advantage of this representation is the fact that the specification is dynamically updated according to the information obtained from the implementation. At the end, if two updated models are not equivalent, possible bugs can be localized and then corrected automatically by analyzing the difference, if possible. Experimental results show the robustness of the proposed technique in comparison with other contemporary methods in terms of the run time and also show that two orders of magnitude average speedup is obtained.

show abstract

Section: Introductionmentioning

confidence: 99%

“…In addition to the above-mentioned methods, there are many methods for verification of dividers specially SRT dividers [1][17] [18] [19]. In general most of them cannot support optimization techniques and in some cases the run time is very high.…”

Section: Introductionmentioning

confidence: 99%

A dynamic specification to automatically debug and correct various divider circuits

Haghbayan

Alizadeh

2016

Integration

View full text Add to dashboard Cite

show abstract

Divider Circuit Verification with Model Checking and Theorem Proving

Kaivola

Aagaard

2000

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Automatic datapath extraction for efficient usage of HDD

Kamhi

Weissberg

Fix

1997

Computer Aided Verification

View full text Add to dashboard Cite

Hybrid Decision Diagrams (HDD) have been proven in Intel to be an important enabler for the formal verification of datapath intensive circuits and in particular the verification of arithmetic units. However, extensive user interaction with the formal verification tool was required in order to use the HDD technology efficiently. The user had to analyze the circuit and its specification and manually partition the signals and operations into control and datapath.In this paper, we will demonstrate how we have made use of the automatic datapath extraction techniques widely used in the synthesis world in order to efficiently integrate HDDs to an SMV-based formal verification system. The intention of this paper is to illustrate how existing technology can help improve the usability and productivity of the formal verification process and enable efficient integration of new technology, in our case HDDs.The system described in this paper, Prover, statically analyzes the model to be verified and partitions the representation of the logic to HDDs and Binary Decision Diagrams (BDDs). Moreover, the partitioning algorithm decides which vector operations will be represented more efficiently as word-level (i.e. using HDD) versus bit-level (i.e using BDD).The new methodology of integrating HDD into the formal verification process increases the productivity of the verification process. At the same time, experiments with Prover show that verification is (both computation and memory usage wise) as efficient as the previously known manual method.1. The reader is referred to Section 4 and [1,2,3,5,12] for detailed description of BDDs, MTBDDs, BMDs and HDDs.

show abstract

Bit-Level Analysis of an SRT Divider Circuit.

Cited by 7 publications

References 10 publications

A dynamic specification to automatically debug and correct various divider circuits

A dynamic specification to automatically debug and correct various divider circuits

Divider Circuit Verification with Model Checking and Theorem Proving

Automatic datapath extraction for efficient usage of HDD

Contact Info

Product

Resources

About